libFirm
gen_ia32_new_nodes.h
1 
9 #ifndef FIRM_BE_IA32_GEN_IA32_NEW_NODES_H
10 #define FIRM_BE_IA32_GEN_IA32_NEW_NODES_H
11 
12 #include "be_types.h"
13 #include "irnode_t.h"
14 #include "ia32_nodes_attr.h"
15 
16 typedef enum ia32_opcodes {
17  iro_ia32_Adc,
18  iro_ia32_Add,
19  iro_ia32_AddMem,
20  iro_ia32_AddSP,
21  iro_ia32_Adds,
22  iro_ia32_And,
23  iro_ia32_AndMem,
24  iro_ia32_Andnp,
25  iro_ia32_Andp,
26  iro_ia32_Breakpoint,
27  iro_ia32_Bsf,
28  iro_ia32_Bsr,
29  iro_ia32_Bswap,
30  iro_ia32_Bswap16,
31  iro_ia32_Bt,
32  iro_ia32_CMovcc,
33  iro_ia32_Call,
34  iro_ia32_ChangeCW,
35  iro_ia32_Cltd,
36  iro_ia32_Cmc,
37  iro_ia32_Cmp,
38  iro_ia32_CmpXChgMem,
39  iro_ia32_Const,
40  iro_ia32_Conv_FP2FP,
41  iro_ia32_Conv_FP2I,
42  iro_ia32_Conv_I2FP,
43  iro_ia32_Conv_I2I,
44  iro_ia32_CopyB,
45  iro_ia32_CopyB_i,
46  iro_ia32_CopyEbpEsp,
47  iro_ia32_CvtSI2SD,
48  iro_ia32_CvtSI2SS,
49  iro_ia32_Cwtl,
50  iro_ia32_Dec,
51  iro_ia32_DecMem,
52  iro_ia32_Div,
53  iro_ia32_Divs,
54  iro_ia32_Enter,
55  iro_ia32_FldCW,
56  iro_ia32_FnstCW,
57  iro_ia32_FnstCWNOP,
58  iro_ia32_FtstFnstsw,
59  iro_ia32_FucomFnstsw,
60  iro_ia32_Fucomi,
61  iro_ia32_FucomppFnstsw,
62  iro_ia32_GetEIP,
63  iro_ia32_IDiv,
64  iro_ia32_IJmp,
65  iro_ia32_IMul,
66  iro_ia32_IMul1OP,
67  iro_ia32_IMulImm,
68  iro_ia32_Immediate,
69  iro_ia32_Inc,
70  iro_ia32_IncMem,
71  iro_ia32_Inport,
72  iro_ia32_Jcc,
73  iro_ia32_Jmp,
74  iro_ia32_LdTls,
75  iro_ia32_Lea,
76  iro_ia32_Leave,
77  iro_ia32_Load,
78  iro_ia32_Maxs,
79  iro_ia32_Mins,
80  iro_ia32_Minus64,
81  iro_ia32_Movd,
82  iro_ia32_Mul,
83  iro_ia32_Muls,
84  iro_ia32_Neg,
85  iro_ia32_NegMem,
86  iro_ia32_NoReg_FP,
87  iro_ia32_NoReg_GP,
88  iro_ia32_NoReg_XMM,
89  iro_ia32_Not,
90  iro_ia32_NotMem,
91  iro_ia32_Or,
92  iro_ia32_OrMem,
93  iro_ia32_Orp,
94  iro_ia32_Outport,
95  iro_ia32_Pop,
96  iro_ia32_PopMem,
97  iro_ia32_Popcnt,
98  iro_ia32_Prefetch,
99  iro_ia32_PrefetchNTA,
100  iro_ia32_PrefetchT0,
101  iro_ia32_PrefetchT1,
102  iro_ia32_PrefetchT2,
103  iro_ia32_PrefetchW,
104  iro_ia32_Pslld,
105  iro_ia32_Psllq,
106  iro_ia32_Psrld,
107  iro_ia32_Push,
108  iro_ia32_PushEax,
109  iro_ia32_Return,
110  iro_ia32_Rol,
111  iro_ia32_RolMem,
112  iro_ia32_Ror,
113  iro_ia32_RorMem,
114  iro_ia32_Sahf,
115  iro_ia32_Sar,
116  iro_ia32_SarMem,
117  iro_ia32_Sbb,
118  iro_ia32_Sbb0,
119  iro_ia32_Setcc,
120  iro_ia32_SetccMem,
121  iro_ia32_Shl,
122  iro_ia32_ShlD,
123  iro_ia32_ShlMem,
124  iro_ia32_Shr,
125  iro_ia32_ShrD,
126  iro_ia32_ShrMem,
127  iro_ia32_Stc,
128  iro_ia32_Store,
129  iro_ia32_Sub,
130  iro_ia32_SubMem,
131  iro_ia32_SubSP,
132  iro_ia32_Subs,
133  iro_ia32_SwitchJmp,
134  iro_ia32_Test,
135  iro_ia32_UD2,
136  iro_ia32_Ucomis,
137  iro_ia32_Xor,
138  iro_ia32_Xor0,
139  iro_ia32_XorHighLow,
140  iro_ia32_XorMem,
141  iro_ia32_Xorp,
142  iro_ia32_emms,
143  iro_ia32_fabs,
144  iro_ia32_fadd,
145  iro_ia32_fchs,
146  iro_ia32_fdiv,
147  iro_ia32_fdup,
148  iro_ia32_femms,
149  iro_ia32_ffreep,
150  iro_ia32_fild,
151  iro_ia32_fist,
152  iro_ia32_fistp,
153  iro_ia32_fisttp,
154  iro_ia32_fld,
155  iro_ia32_fld1,
156  iro_ia32_fldl2e,
157  iro_ia32_fldl2t,
158  iro_ia32_fldlg2,
159  iro_ia32_fldln2,
160  iro_ia32_fldpi,
161  iro_ia32_fldz,
162  iro_ia32_fmul,
163  iro_ia32_fpop,
164  iro_ia32_fst,
165  iro_ia32_fstp,
166  iro_ia32_fsub,
167  iro_ia32_fxch,
168  iro_ia32_l_Adc,
169  iro_ia32_l_Add,
170  iro_ia32_l_FloattoLL,
171  iro_ia32_l_IMul,
172  iro_ia32_l_LLtoFloat,
173  iro_ia32_l_Minus64,
174  iro_ia32_l_Mul,
175  iro_ia32_l_Sbb,
176  iro_ia32_l_Sub,
177  iro_ia32_xAllOnes,
178  iro_ia32_xLoad,
179  iro_ia32_xPzero,
180  iro_ia32_xStore,
181  iro_ia32_xZero,
182  iro_ia32_xxLoad,
183  iro_ia32_xxStore,
184  iro_ia32_last
185 } ia32_opcodes;
186 
187 
188 int is_ia32_irn(const ir_node *node);
189 int is_ia32_op(const ir_op *op);
190 
191 int get_ia32_irn_opcode(const ir_node *node);
192 void ia32_create_opcodes(void);
193 void ia32_free_opcodes(void);
194 
195 extern ir_op *op_ia32_Adc;
196 
197 static inline bool is_ia32_Adc(ir_node const *const n)
198 {
199  return get_irn_op(n) == op_ia32_Adc;
200 }
201 
205 ir_node *new_bd_ia32_Adc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *eflags, x86_insn_size_t size);
206 
207 extern ir_op *op_ia32_Add;
208 
209 static inline bool is_ia32_Add(ir_node const *const n)
210 {
211  return get_irn_op(n) == op_ia32_Add;
212 }
213 
217 ir_node *new_bd_ia32_Add(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
221 ir_node *new_bd_ia32_Add_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
222 
223 extern ir_op *op_ia32_AddMem;
224 
225 static inline bool is_ia32_AddMem(ir_node const *const n)
226 {
227  return get_irn_op(n) == op_ia32_AddMem;
228 }
229 
233 ir_node *new_bd_ia32_AddMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
237 ir_node *new_bd_ia32_AddMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
238 
239 extern ir_op *op_ia32_AddSP;
240 
241 static inline bool is_ia32_AddSP(ir_node const *const n)
242 {
243  return get_irn_op(n) == op_ia32_AddSP;
244 }
245 
249 ir_node *new_bd_ia32_AddSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *amount);
250 
251 extern ir_op *op_ia32_Adds;
252 
253 static inline bool is_ia32_Adds(ir_node const *const n)
254 {
255  return get_irn_op(n) == op_ia32_Adds;
256 }
257 
261 ir_node *new_bd_ia32_Adds(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
262 
263 extern ir_op *op_ia32_And;
264 
265 static inline bool is_ia32_And(ir_node const *const n)
266 {
267  return get_irn_op(n) == op_ia32_And;
268 }
269 
273 ir_node *new_bd_ia32_And(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
277 ir_node *new_bd_ia32_And_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
278 
279 extern ir_op *op_ia32_AndMem;
280 
281 static inline bool is_ia32_AndMem(ir_node const *const n)
282 {
283  return get_irn_op(n) == op_ia32_AndMem;
284 }
285 
289 ir_node *new_bd_ia32_AndMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
293 ir_node *new_bd_ia32_AndMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
294 
295 extern ir_op *op_ia32_Andnp;
296 
297 static inline bool is_ia32_Andnp(ir_node const *const n)
298 {
299  return get_irn_op(n) == op_ia32_Andnp;
300 }
301 
305 ir_node *new_bd_ia32_Andnp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
306 
307 extern ir_op *op_ia32_Andp;
308 
309 static inline bool is_ia32_Andp(ir_node const *const n)
310 {
311  return get_irn_op(n) == op_ia32_Andp;
312 }
313 
317 ir_node *new_bd_ia32_Andp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
318 
319 extern ir_op *op_ia32_Breakpoint;
320 
321 static inline bool is_ia32_Breakpoint(ir_node const *const n)
322 {
323  return get_irn_op(n) == op_ia32_Breakpoint;
324 }
325 
329 ir_node *new_bd_ia32_Breakpoint(dbg_info *dbgi, ir_node *block, ir_node *mem);
330 
331 extern ir_op *op_ia32_Bsf;
332 
333 static inline bool is_ia32_Bsf(ir_node const *const n)
334 {
335  return get_irn_op(n) == op_ia32_Bsf;
336 }
337 
341 ir_node *new_bd_ia32_Bsf(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size);
342 
343 extern ir_op *op_ia32_Bsr;
344 
345 static inline bool is_ia32_Bsr(ir_node const *const n)
346 {
347  return get_irn_op(n) == op_ia32_Bsr;
348 }
349 
353 ir_node *new_bd_ia32_Bsr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size);
354 
355 extern ir_op *op_ia32_Bswap;
356 
357 static inline bool is_ia32_Bswap(ir_node const *const n)
358 {
359  return get_irn_op(n) == op_ia32_Bswap;
360 }
361 
365 ir_node *new_bd_ia32_Bswap(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size);
366 
367 extern ir_op *op_ia32_Bswap16;
368 
369 static inline bool is_ia32_Bswap16(ir_node const *const n)
370 {
371  return get_irn_op(n) == op_ia32_Bswap16;
372 }
373 
377 ir_node *new_bd_ia32_Bswap16(dbg_info *dbgi, ir_node *block, ir_node *val);
378 
379 extern ir_op *op_ia32_Bt;
380 
381 static inline bool is_ia32_Bt(ir_node const *const n)
382 {
383  return get_irn_op(n) == op_ia32_Bt;
384 }
385 
389 ir_node *new_bd_ia32_Bt(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, x86_insn_size_t size);
390 
391 extern ir_op *op_ia32_CMovcc;
392 
393 static inline bool is_ia32_CMovcc(ir_node const *const n)
394 {
395  return get_irn_op(n) == op_ia32_CMovcc;
396 }
397 
401 ir_node *new_bd_ia32_CMovcc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val_false, ir_node *val_true, ir_node *eflags, x86_insn_size_t size, x86_condition_code_t condition_code);
402 
403 extern ir_op *op_ia32_Call;
404 
405 static inline bool is_ia32_Call(ir_node const *const n)
406 {
407  return get_irn_op(n) == op_ia32_Call;
408 }
409 
413 ir_node *new_bd_ia32_Call(dbg_info *dbgi, ir_node *block, int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs, int n_res, uint8_t pop, uint8_t n_reg_results);
414 
415 extern ir_op *op_ia32_ChangeCW;
416 
417 static inline bool is_ia32_ChangeCW(ir_node const *const n)
418 {
419  return get_irn_op(n) == op_ia32_ChangeCW;
420 }
421 
425 ir_node *new_bd_ia32_ChangeCW(dbg_info *dbgi, ir_node *block);
426 
427 extern ir_op *op_ia32_Cltd;
428 
429 static inline bool is_ia32_Cltd(ir_node const *const n)
430 {
431  return get_irn_op(n) == op_ia32_Cltd;
432 }
433 
437 ir_node *new_bd_ia32_Cltd(dbg_info *dbgi, ir_node *block, ir_node *val);
438 
439 extern ir_op *op_ia32_Cmc;
440 
441 static inline bool is_ia32_Cmc(ir_node const *const n)
442 {
443  return get_irn_op(n) == op_ia32_Cmc;
444 }
445 
449 ir_node *new_bd_ia32_Cmc(dbg_info *dbgi, ir_node *block, ir_node *op0);
450 
451 extern ir_op *op_ia32_Cmp;
452 
453 static inline bool is_ia32_Cmp(ir_node const *const n)
454 {
455  return get_irn_op(n) == op_ia32_Cmp;
456 }
457 
461 ir_node *new_bd_ia32_Cmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted);
465 ir_node *new_bd_ia32_Cmp_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted);
466 
467 extern ir_op *op_ia32_CmpXChgMem;
468 
469 static inline bool is_ia32_CmpXChgMem(ir_node const *const n)
470 {
471  return get_irn_op(n) == op_ia32_CmpXChgMem;
472 }
473 
477 ir_node *new_bd_ia32_CmpXChgMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *old, ir_node *new, x86_insn_size_t size);
478 
479 extern ir_op *op_ia32_Const;
480 
481 static inline bool is_ia32_Const(ir_node const *const n)
482 {
483  return get_irn_op(n) == op_ia32_Const;
484 }
485 
489 ir_node *new_bd_ia32_Const(dbg_info *dbgi, ir_node *block, const x86_imm32_t *imm);
490 
491 extern ir_op *op_ia32_Conv_FP2FP;
492 
493 static inline bool is_ia32_Conv_FP2FP(ir_node const *const n)
494 {
495  return get_irn_op(n) == op_ia32_Conv_FP2FP;
496 }
497 
501 ir_node *new_bd_ia32_Conv_FP2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
502 
503 extern ir_op *op_ia32_Conv_FP2I;
504 
505 static inline bool is_ia32_Conv_FP2I(ir_node const *const n)
506 {
507  return get_irn_op(n) == op_ia32_Conv_FP2I;
508 }
509 
513 ir_node *new_bd_ia32_Conv_FP2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
514 
515 extern ir_op *op_ia32_Conv_I2FP;
516 
517 static inline bool is_ia32_Conv_I2FP(ir_node const *const n)
518 {
519  return get_irn_op(n) == op_ia32_Conv_I2FP;
520 }
521 
525 ir_node *new_bd_ia32_Conv_I2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
526 
527 extern ir_op *op_ia32_Conv_I2I;
528 
529 static inline bool is_ia32_Conv_I2I(ir_node const *const n)
530 {
531  return get_irn_op(n) == op_ia32_Conv_I2I;
532 }
533 
537 ir_node *new_bd_ia32_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size, bool sign_extend);
541 ir_node *new_bd_ia32_Conv_I2I_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size, bool sign_extend);
542 
543 extern ir_op *op_ia32_CopyB;
544 
545 static inline bool is_ia32_CopyB(ir_node const *const n)
546 {
547  return get_irn_op(n) == op_ia32_CopyB;
548 }
549 
553 ir_node *new_bd_ia32_CopyB(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *count, ir_node *mem, unsigned size);
554 
555 extern ir_op *op_ia32_CopyB_i;
556 
557 static inline bool is_ia32_CopyB_i(ir_node const *const n)
558 {
559  return get_irn_op(n) == op_ia32_CopyB_i;
560 }
561 
565 ir_node *new_bd_ia32_CopyB_i(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *mem, unsigned size);
566 
567 extern ir_op *op_ia32_CopyEbpEsp;
568 
569 static inline bool is_ia32_CopyEbpEsp(ir_node const *const n)
570 {
571  return get_irn_op(n) == op_ia32_CopyEbpEsp;
572 }
573 
577 ir_node *new_bd_ia32_CopyEbpEsp(dbg_info *dbgi, ir_node *block, ir_node *ebp);
578 
579 extern ir_op *op_ia32_CvtSI2SD;
580 
581 static inline bool is_ia32_CvtSI2SD(ir_node const *const n)
582 {
583  return get_irn_op(n) == op_ia32_CvtSI2SD;
584 }
585 
589 ir_node *new_bd_ia32_CvtSI2SD(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
590 
591 extern ir_op *op_ia32_CvtSI2SS;
592 
593 static inline bool is_ia32_CvtSI2SS(ir_node const *const n)
594 {
595  return get_irn_op(n) == op_ia32_CvtSI2SS;
596 }
597 
601 ir_node *new_bd_ia32_CvtSI2SS(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
602 
603 extern ir_op *op_ia32_Cwtl;
604 
605 static inline bool is_ia32_Cwtl(ir_node const *const n)
606 {
607  return get_irn_op(n) == op_ia32_Cwtl;
608 }
609 
613 ir_node *new_bd_ia32_Cwtl(dbg_info *dbgi, ir_node *block, ir_node *val);
614 
615 extern ir_op *op_ia32_Dec;
616 
617 static inline bool is_ia32_Dec(ir_node const *const n)
618 {
619  return get_irn_op(n) == op_ia32_Dec;
620 }
621 
625 ir_node *new_bd_ia32_Dec(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size);
626 
627 extern ir_op *op_ia32_DecMem;
628 
629 static inline bool is_ia32_DecMem(ir_node const *const n)
630 {
631  return get_irn_op(n) == op_ia32_DecMem;
632 }
633 
637 ir_node *new_bd_ia32_DecMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size);
638 
639 extern ir_op *op_ia32_Div;
640 
641 static inline bool is_ia32_Div(ir_node const *const n)
642 {
643  return get_irn_op(n) == op_ia32_Div;
644 }
645 
649 ir_node *new_bd_ia32_Div(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high, x86_insn_size_t size);
650 
651 extern ir_op *op_ia32_Divs;
652 
653 static inline bool is_ia32_Divs(ir_node const *const n)
654 {
655  return get_irn_op(n) == op_ia32_Divs;
656 }
657 
661 ir_node *new_bd_ia32_Divs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
662 
663 extern ir_op *op_ia32_Enter;
664 
665 static inline bool is_ia32_Enter(ir_node const *const n)
666 {
667  return get_irn_op(n) == op_ia32_Enter;
668 }
669 
673 ir_node *new_bd_ia32_Enter(dbg_info *dbgi, ir_node *block, ir_node *op0);
674 
675 extern ir_op *op_ia32_FldCW;
676 
677 static inline bool is_ia32_FldCW(ir_node const *const n)
678 {
679  return get_irn_op(n) == op_ia32_FldCW;
680 }
681 
685 ir_node *new_bd_ia32_FldCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
686 
687 extern ir_op *op_ia32_FnstCW;
688 
689 static inline bool is_ia32_FnstCW(ir_node const *const n)
690 {
691  return get_irn_op(n) == op_ia32_FnstCW;
692 }
693 
697 ir_node *new_bd_ia32_FnstCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *fpcw);
698 
699 extern ir_op *op_ia32_FnstCWNOP;
700 
701 static inline bool is_ia32_FnstCWNOP(ir_node const *const n)
702 {
703  return get_irn_op(n) == op_ia32_FnstCWNOP;
704 }
705 
709 ir_node *new_bd_ia32_FnstCWNOP(dbg_info *dbgi, ir_node *block, ir_node *fpcw);
710 
711 extern ir_op *op_ia32_FtstFnstsw;
712 
713 static inline bool is_ia32_FtstFnstsw(ir_node const *const n)
714 {
715  return get_irn_op(n) == op_ia32_FtstFnstsw;
716 }
717 
721 ir_node *new_bd_ia32_FtstFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, bool ins_permuted);
722 
723 extern ir_op *op_ia32_FucomFnstsw;
724 
725 static inline bool is_ia32_FucomFnstsw(ir_node const *const n)
726 {
727  return get_irn_op(n) == op_ia32_FucomFnstsw;
728 }
729 
733 ir_node *new_bd_ia32_FucomFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted);
734 
735 extern ir_op *op_ia32_Fucomi;
736 
737 static inline bool is_ia32_Fucomi(ir_node const *const n)
738 {
739  return get_irn_op(n) == op_ia32_Fucomi;
740 }
741 
745 ir_node *new_bd_ia32_Fucomi(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted);
746 
747 extern ir_op *op_ia32_FucomppFnstsw;
748 
749 static inline bool is_ia32_FucomppFnstsw(ir_node const *const n)
750 {
751  return get_irn_op(n) == op_ia32_FucomppFnstsw;
752 }
753 
757 ir_node *new_bd_ia32_FucomppFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted);
758 
759 extern ir_op *op_ia32_GetEIP;
760 
761 static inline bool is_ia32_GetEIP(ir_node const *const n)
762 {
763  return get_irn_op(n) == op_ia32_GetEIP;
764 }
765 
769 ir_node *new_bd_ia32_GetEIP(dbg_info *dbgi, ir_node *block);
770 
771 extern ir_op *op_ia32_IDiv;
772 
773 static inline bool is_ia32_IDiv(ir_node const *const n)
774 {
775  return get_irn_op(n) == op_ia32_IDiv;
776 }
777 
781 ir_node *new_bd_ia32_IDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high, x86_insn_size_t size);
782 
783 extern ir_op *op_ia32_IJmp;
784 
785 static inline bool is_ia32_IJmp(ir_node const *const n)
786 {
787  return get_irn_op(n) == op_ia32_IJmp;
788 }
789 
793 ir_node *new_bd_ia32_IJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *target);
794 
795 extern ir_op *op_ia32_IMul;
796 
797 static inline bool is_ia32_IMul(ir_node const *const n)
798 {
799  return get_irn_op(n) == op_ia32_IMul;
800 }
801 
805 ir_node *new_bd_ia32_IMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
809 ir_node *new_bd_ia32_IMul_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
810 
811 extern ir_op *op_ia32_IMul1OP;
812 
813 static inline bool is_ia32_IMul1OP(ir_node const *const n)
814 {
815  return get_irn_op(n) == op_ia32_IMul1OP;
816 }
817 
821 ir_node *new_bd_ia32_IMul1OP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
822 
823 extern ir_op *op_ia32_IMulImm;
824 
825 static inline bool is_ia32_IMulImm(ir_node const *const n)
826 {
827  return get_irn_op(n) == op_ia32_IMulImm;
828 }
829 
833 ir_node *new_bd_ia32_IMulImm(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
834 
835 extern ir_op *op_ia32_Immediate;
836 
837 static inline bool is_ia32_Immediate(ir_node const *const n)
838 {
839  return get_irn_op(n) == op_ia32_Immediate;
840 }
841 
845 ir_node *new_bd_ia32_Immediate(dbg_info *dbgi, ir_node *block, const x86_imm32_t *imm);
846 
847 extern ir_op *op_ia32_Inc;
848 
849 static inline bool is_ia32_Inc(ir_node const *const n)
850 {
851  return get_irn_op(n) == op_ia32_Inc;
852 }
853 
857 ir_node *new_bd_ia32_Inc(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size);
858 
859 extern ir_op *op_ia32_IncMem;
860 
861 static inline bool is_ia32_IncMem(ir_node const *const n)
862 {
863  return get_irn_op(n) == op_ia32_IncMem;
864 }
865 
869 ir_node *new_bd_ia32_IncMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size);
870 
871 extern ir_op *op_ia32_Inport;
872 
873 static inline bool is_ia32_Inport(ir_node const *const n)
874 {
875  return get_irn_op(n) == op_ia32_Inport;
876 }
877 
881 ir_node *new_bd_ia32_Inport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *mem, x86_insn_size_t size);
882 
883 extern ir_op *op_ia32_Jcc;
884 
885 static inline bool is_ia32_Jcc(ir_node const *const n)
886 {
887  return get_irn_op(n) == op_ia32_Jcc;
888 }
889 
893 ir_node *new_bd_ia32_Jcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, x86_condition_code_t condition_code);
894 
895 extern ir_op *op_ia32_Jmp;
896 
897 static inline bool is_ia32_Jmp(ir_node const *const n)
898 {
899  return get_irn_op(n) == op_ia32_Jmp;
900 }
901 
905 ir_node *new_bd_ia32_Jmp(dbg_info *dbgi, ir_node *block);
906 
907 extern ir_op *op_ia32_LdTls;
908 
909 static inline bool is_ia32_LdTls(ir_node const *const n)
910 {
911  return get_irn_op(n) == op_ia32_LdTls;
912 }
913 
917 ir_node *new_bd_ia32_LdTls(dbg_info *dbgi, ir_node *block);
918 
919 extern ir_op *op_ia32_Lea;
920 
921 static inline bool is_ia32_Lea(ir_node const *const n)
922 {
923  return get_irn_op(n) == op_ia32_Lea;
924 }
925 
929 ir_node *new_bd_ia32_Lea(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index);
930 
931 extern ir_op *op_ia32_Leave;
932 
933 static inline bool is_ia32_Leave(ir_node const *const n)
934 {
935  return get_irn_op(n) == op_ia32_Leave;
936 }
937 
941 ir_node *new_bd_ia32_Leave(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1);
942 
943 extern ir_op *op_ia32_Load;
944 
945 static inline bool is_ia32_Load(ir_node const *const n)
946 {
947  return get_irn_op(n) == op_ia32_Load;
948 }
949 
953 ir_node *new_bd_ia32_Load(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size, bool sign_extend);
954 
955 extern ir_op *op_ia32_Maxs;
956 
957 static inline bool is_ia32_Maxs(ir_node const *const n)
958 {
959  return get_irn_op(n) == op_ia32_Maxs;
960 }
961 
965 ir_node *new_bd_ia32_Maxs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
966 
967 extern ir_op *op_ia32_Mins;
968 
969 static inline bool is_ia32_Mins(ir_node const *const n)
970 {
971  return get_irn_op(n) == op_ia32_Mins;
972 }
973 
977 ir_node *new_bd_ia32_Mins(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
978 
979 extern ir_op *op_ia32_Minus64;
980 
981 static inline bool is_ia32_Minus64(ir_node const *const n)
982 {
983  return get_irn_op(n) == op_ia32_Minus64;
984 }
985 
989 ir_node *new_bd_ia32_Minus64(dbg_info *dbgi, ir_node *block, ir_node *low, ir_node *high);
990 
991 extern ir_op *op_ia32_Movd;
992 
993 static inline bool is_ia32_Movd(ir_node const *const n)
994 {
995  return get_irn_op(n) == op_ia32_Movd;
996 }
997 
1001 ir_node *new_bd_ia32_Movd(dbg_info *dbgi, ir_node *block, ir_node *op0);
1002 
1003 extern ir_op *op_ia32_Mul;
1004 
1005 static inline bool is_ia32_Mul(ir_node const *const n)
1006 {
1007  return get_irn_op(n) == op_ia32_Mul;
1008 }
1009 
1013 ir_node *new_bd_ia32_Mul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
1014 
1015 extern ir_op *op_ia32_Muls;
1016 
1017 static inline bool is_ia32_Muls(ir_node const *const n)
1018 {
1019  return get_irn_op(n) == op_ia32_Muls;
1020 }
1021 
1025 ir_node *new_bd_ia32_Muls(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
1026 
1027 extern ir_op *op_ia32_Neg;
1028 
1029 static inline bool is_ia32_Neg(ir_node const *const n)
1030 {
1031  return get_irn_op(n) == op_ia32_Neg;
1032 }
1033 
1037 ir_node *new_bd_ia32_Neg(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size);
1038 
1039 extern ir_op *op_ia32_NegMem;
1040 
1041 static inline bool is_ia32_NegMem(ir_node const *const n)
1042 {
1043  return get_irn_op(n) == op_ia32_NegMem;
1044 }
1045 
1049 ir_node *new_bd_ia32_NegMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size);
1050 
1051 extern ir_op *op_ia32_NoReg_FP;
1052 
1053 static inline bool is_ia32_NoReg_FP(ir_node const *const n)
1054 {
1055  return get_irn_op(n) == op_ia32_NoReg_FP;
1056 }
1057 
1061 ir_node *new_bd_ia32_NoReg_FP(dbg_info *dbgi, ir_node *block);
1062 
1063 extern ir_op *op_ia32_NoReg_GP;
1064 
1065 static inline bool is_ia32_NoReg_GP(ir_node const *const n)
1066 {
1067  return get_irn_op(n) == op_ia32_NoReg_GP;
1068 }
1069 
1073 ir_node *new_bd_ia32_NoReg_GP(dbg_info *dbgi, ir_node *block);
1074 
1075 extern ir_op *op_ia32_NoReg_XMM;
1076 
1077 static inline bool is_ia32_NoReg_XMM(ir_node const *const n)
1078 {
1079  return get_irn_op(n) == op_ia32_NoReg_XMM;
1080 }
1081 
1085 ir_node *new_bd_ia32_NoReg_XMM(dbg_info *dbgi, ir_node *block);
1086 
1087 extern ir_op *op_ia32_Not;
1088 
1089 static inline bool is_ia32_Not(ir_node const *const n)
1090 {
1091  return get_irn_op(n) == op_ia32_Not;
1092 }
1093 
1097 ir_node *new_bd_ia32_Not(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size);
1101 ir_node *new_bd_ia32_Not_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size);
1102 
1103 extern ir_op *op_ia32_NotMem;
1104 
1105 static inline bool is_ia32_NotMem(ir_node const *const n)
1106 {
1107  return get_irn_op(n) == op_ia32_NotMem;
1108 }
1109 
1113 ir_node *new_bd_ia32_NotMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size);
1114 
1115 extern ir_op *op_ia32_Or;
1116 
1117 static inline bool is_ia32_Or(ir_node const *const n)
1118 {
1119  return get_irn_op(n) == op_ia32_Or;
1120 }
1121 
1125 ir_node *new_bd_ia32_Or(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
1129 ir_node *new_bd_ia32_Or_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
1130 
1131 extern ir_op *op_ia32_OrMem;
1132 
1133 static inline bool is_ia32_OrMem(ir_node const *const n)
1134 {
1135  return get_irn_op(n) == op_ia32_OrMem;
1136 }
1137 
1141 ir_node *new_bd_ia32_OrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1145 ir_node *new_bd_ia32_OrMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1146 
1147 extern ir_op *op_ia32_Orp;
1148 
1149 static inline bool is_ia32_Orp(ir_node const *const n)
1150 {
1151  return get_irn_op(n) == op_ia32_Orp;
1152 }
1153 
1157 ir_node *new_bd_ia32_Orp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
1158 
1159 extern ir_op *op_ia32_Outport;
1160 
1161 static inline bool is_ia32_Outport(ir_node const *const n)
1162 {
1163  return get_irn_op(n) == op_ia32_Outport;
1164 }
1165 
1169 ir_node *new_bd_ia32_Outport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *value, ir_node *mem, x86_insn_size_t size);
1170 
1171 extern ir_op *op_ia32_Pop;
1172 
1173 static inline bool is_ia32_Pop(ir_node const *const n)
1174 {
1175  return get_irn_op(n) == op_ia32_Pop;
1176 }
1177 
1181 ir_node *new_bd_ia32_Pop(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack, x86_insn_size_t size);
1185 ir_node *new_bd_ia32_Pop_ebp(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack, x86_insn_size_t size);
1186 
1187 extern ir_op *op_ia32_PopMem;
1188 
1189 static inline bool is_ia32_PopMem(ir_node const *const n)
1190 {
1191  return get_irn_op(n) == op_ia32_PopMem;
1192 }
1193 
1197 ir_node *new_bd_ia32_PopMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, x86_insn_size_t size);
1198 
1199 extern ir_op *op_ia32_Popcnt;
1200 
1201 static inline bool is_ia32_Popcnt(ir_node const *const n)
1202 {
1203  return get_irn_op(n) == op_ia32_Popcnt;
1204 }
1205 
1209 ir_node *new_bd_ia32_Popcnt(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size);
1210 
1211 extern ir_op *op_ia32_Prefetch;
1212 
1213 static inline bool is_ia32_Prefetch(ir_node const *const n)
1214 {
1215  return get_irn_op(n) == op_ia32_Prefetch;
1216 }
1217 
1221 ir_node *new_bd_ia32_Prefetch(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1222 
1223 extern ir_op *op_ia32_PrefetchNTA;
1224 
1225 static inline bool is_ia32_PrefetchNTA(ir_node const *const n)
1226 {
1227  return get_irn_op(n) == op_ia32_PrefetchNTA;
1228 }
1229 
1233 ir_node *new_bd_ia32_PrefetchNTA(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1234 
1235 extern ir_op *op_ia32_PrefetchT0;
1236 
1237 static inline bool is_ia32_PrefetchT0(ir_node const *const n)
1238 {
1239  return get_irn_op(n) == op_ia32_PrefetchT0;
1240 }
1241 
1245 ir_node *new_bd_ia32_PrefetchT0(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1246 
1247 extern ir_op *op_ia32_PrefetchT1;
1248 
1249 static inline bool is_ia32_PrefetchT1(ir_node const *const n)
1250 {
1251  return get_irn_op(n) == op_ia32_PrefetchT1;
1252 }
1253 
1257 ir_node *new_bd_ia32_PrefetchT1(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1258 
1259 extern ir_op *op_ia32_PrefetchT2;
1260 
1261 static inline bool is_ia32_PrefetchT2(ir_node const *const n)
1262 {
1263  return get_irn_op(n) == op_ia32_PrefetchT2;
1264 }
1265 
1269 ir_node *new_bd_ia32_PrefetchT2(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1270 
1271 extern ir_op *op_ia32_PrefetchW;
1272 
1273 static inline bool is_ia32_PrefetchW(ir_node const *const n)
1274 {
1275  return get_irn_op(n) == op_ia32_PrefetchW;
1276 }
1277 
1281 ir_node *new_bd_ia32_PrefetchW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
1282 
1283 extern ir_op *op_ia32_Pslld;
1284 
1285 static inline bool is_ia32_Pslld(ir_node const *const n)
1286 {
1287  return get_irn_op(n) == op_ia32_Pslld;
1288 }
1289 
1293 ir_node *new_bd_ia32_Pslld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size);
1294 
1295 extern ir_op *op_ia32_Psllq;
1296 
1297 static inline bool is_ia32_Psllq(ir_node const *const n)
1298 {
1299  return get_irn_op(n) == op_ia32_Psllq;
1300 }
1301 
1305 ir_node *new_bd_ia32_Psllq(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size);
1306 
1307 extern ir_op *op_ia32_Psrld;
1308 
1309 static inline bool is_ia32_Psrld(ir_node const *const n)
1310 {
1311  return get_irn_op(n) == op_ia32_Psrld;
1312 }
1313 
1317 ir_node *new_bd_ia32_Psrld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size);
1318 
1319 extern ir_op *op_ia32_Push;
1320 
1321 static inline bool is_ia32_Push(ir_node const *const n)
1322 {
1323  return get_irn_op(n) == op_ia32_Push;
1324 }
1325 
1329 ir_node *new_bd_ia32_Push(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *stack, x86_insn_size_t size);
1330 
1331 extern ir_op *op_ia32_PushEax;
1332 
1333 static inline bool is_ia32_PushEax(ir_node const *const n)
1334 {
1335  return get_irn_op(n) == op_ia32_PushEax;
1336 }
1337 
1341 ir_node *new_bd_ia32_PushEax(dbg_info *dbgi, ir_node *block, ir_node *stack);
1342 
1343 extern ir_op *op_ia32_Return;
1344 
1345 static inline bool is_ia32_Return(ir_node const *const n)
1346 {
1347  return get_irn_op(n) == op_ia32_Return;
1348 }
1349 
1353 ir_node *new_bd_ia32_Return(dbg_info *dbgi, ir_node *block, int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs, uint16_t pop);
1354 
1355 extern ir_op *op_ia32_Rol;
1356 
1357 static inline bool is_ia32_Rol(ir_node const *const n)
1358 {
1359  return get_irn_op(n) == op_ia32_Rol;
1360 }
1361 
1365 ir_node *new_bd_ia32_Rol(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1369 ir_node *new_bd_ia32_Rol_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1370 
1371 extern ir_op *op_ia32_RolMem;
1372 
1373 static inline bool is_ia32_RolMem(ir_node const *const n)
1374 {
1375  return get_irn_op(n) == op_ia32_RolMem;
1376 }
1377 
1381 ir_node *new_bd_ia32_RolMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size);
1382 
1383 extern ir_op *op_ia32_Ror;
1384 
1385 static inline bool is_ia32_Ror(ir_node const *const n)
1386 {
1387  return get_irn_op(n) == op_ia32_Ror;
1388 }
1389 
1393 ir_node *new_bd_ia32_Ror(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1397 ir_node *new_bd_ia32_Ror_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1398 
1399 extern ir_op *op_ia32_RorMem;
1400 
1401 static inline bool is_ia32_RorMem(ir_node const *const n)
1402 {
1403  return get_irn_op(n) == op_ia32_RorMem;
1404 }
1405 
1409 ir_node *new_bd_ia32_RorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size);
1410 
1411 extern ir_op *op_ia32_Sahf;
1412 
1413 static inline bool is_ia32_Sahf(ir_node const *const n)
1414 {
1415  return get_irn_op(n) == op_ia32_Sahf;
1416 }
1417 
1421 ir_node *new_bd_ia32_Sahf(dbg_info *dbgi, ir_node *block, ir_node *val);
1422 
1423 extern ir_op *op_ia32_Sar;
1424 
1425 static inline bool is_ia32_Sar(ir_node const *const n)
1426 {
1427  return get_irn_op(n) == op_ia32_Sar;
1428 }
1429 
1433 ir_node *new_bd_ia32_Sar(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1437 ir_node *new_bd_ia32_Sar_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1438 
1439 extern ir_op *op_ia32_SarMem;
1440 
1441 static inline bool is_ia32_SarMem(ir_node const *const n)
1442 {
1443  return get_irn_op(n) == op_ia32_SarMem;
1444 }
1445 
1449 ir_node *new_bd_ia32_SarMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size);
1450 
1451 extern ir_op *op_ia32_Sbb;
1452 
1453 static inline bool is_ia32_Sbb(ir_node const *const n)
1454 {
1455  return get_irn_op(n) == op_ia32_Sbb;
1456 }
1457 
1461 ir_node *new_bd_ia32_Sbb(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, x86_insn_size_t size);
1462 
1463 extern ir_op *op_ia32_Sbb0;
1464 
1465 static inline bool is_ia32_Sbb0(ir_node const *const n)
1466 {
1467  return get_irn_op(n) == op_ia32_Sbb0;
1468 }
1469 
1473 ir_node *new_bd_ia32_Sbb0(dbg_info *dbgi, ir_node *block, ir_node *op0, x86_insn_size_t size);
1474 
1475 extern ir_op *op_ia32_Setcc;
1476 
1477 static inline bool is_ia32_Setcc(ir_node const *const n)
1478 {
1479  return get_irn_op(n) == op_ia32_Setcc;
1480 }
1481 
1485 ir_node *new_bd_ia32_Setcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, x86_condition_code_t condition_code);
1486 
1487 extern ir_op *op_ia32_SetccMem;
1488 
1489 static inline bool is_ia32_SetccMem(ir_node const *const n)
1490 {
1491  return get_irn_op(n) == op_ia32_SetccMem;
1492 }
1493 
1497 ir_node *new_bd_ia32_SetccMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *eflags, x86_condition_code_t condition_code);
1498 
1499 extern ir_op *op_ia32_Shl;
1500 
1501 static inline bool is_ia32_Shl(ir_node const *const n)
1502 {
1503  return get_irn_op(n) == op_ia32_Shl;
1504 }
1505 
1509 ir_node *new_bd_ia32_Shl(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1513 ir_node *new_bd_ia32_Shl_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1514 
1515 extern ir_op *op_ia32_ShlD;
1516 
1517 static inline bool is_ia32_ShlD(ir_node const *const n)
1518 {
1519  return get_irn_op(n) == op_ia32_ShlD;
1520 }
1521 
1525 ir_node *new_bd_ia32_ShlD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count);
1529 ir_node *new_bd_ia32_ShlD_imm(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count);
1530 
1531 extern ir_op *op_ia32_ShlMem;
1532 
1533 static inline bool is_ia32_ShlMem(ir_node const *const n)
1534 {
1535  return get_irn_op(n) == op_ia32_ShlMem;
1536 }
1537 
1541 ir_node *new_bd_ia32_ShlMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size);
1542 
1543 extern ir_op *op_ia32_Shr;
1544 
1545 static inline bool is_ia32_Shr(ir_node const *const n)
1546 {
1547  return get_irn_op(n) == op_ia32_Shr;
1548 }
1549 
1553 ir_node *new_bd_ia32_Shr(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1557 ir_node *new_bd_ia32_Shr_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size);
1558 
1559 extern ir_op *op_ia32_ShrD;
1560 
1561 static inline bool is_ia32_ShrD(ir_node const *const n)
1562 {
1563  return get_irn_op(n) == op_ia32_ShrD;
1564 }
1565 
1569 ir_node *new_bd_ia32_ShrD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count);
1573 ir_node *new_bd_ia32_ShrD_imm(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count);
1574 
1575 extern ir_op *op_ia32_ShrMem;
1576 
1577 static inline bool is_ia32_ShrMem(ir_node const *const n)
1578 {
1579  return get_irn_op(n) == op_ia32_ShrMem;
1580 }
1581 
1585 ir_node *new_bd_ia32_ShrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size);
1586 
1587 extern ir_op *op_ia32_Stc;
1588 
1589 static inline bool is_ia32_Stc(ir_node const *const n)
1590 {
1591  return get_irn_op(n) == op_ia32_Stc;
1592 }
1593 
1597 ir_node *new_bd_ia32_Stc(dbg_info *dbgi, ir_node *block);
1598 
1599 extern ir_op *op_ia32_Store;
1600 
1601 static inline bool is_ia32_Store(ir_node const *const n)
1602 {
1603  return get_irn_op(n) == op_ia32_Store;
1604 }
1605 
1609 ir_node *new_bd_ia32_Store(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1613 ir_node *new_bd_ia32_Store_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1614 
1615 extern ir_op *op_ia32_Sub;
1616 
1617 static inline bool is_ia32_Sub(ir_node const *const n)
1618 {
1619  return get_irn_op(n) == op_ia32_Sub;
1620 }
1621 
1625 ir_node *new_bd_ia32_Sub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size);
1629 ir_node *new_bd_ia32_Sub_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size);
1630 
1631 extern ir_op *op_ia32_SubMem;
1632 
1633 static inline bool is_ia32_SubMem(ir_node const *const n)
1634 {
1635  return get_irn_op(n) == op_ia32_SubMem;
1636 }
1637 
1641 ir_node *new_bd_ia32_SubMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1645 ir_node *new_bd_ia32_SubMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1646 
1647 extern ir_op *op_ia32_SubSP;
1648 
1649 static inline bool is_ia32_SubSP(ir_node const *const n)
1650 {
1651  return get_irn_op(n) == op_ia32_SubSP;
1652 }
1653 
1657 ir_node *new_bd_ia32_SubSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *amount);
1658 
1659 extern ir_op *op_ia32_Subs;
1660 
1661 static inline bool is_ia32_Subs(ir_node const *const n)
1662 {
1663  return get_irn_op(n) == op_ia32_Subs;
1664 }
1665 
1669 ir_node *new_bd_ia32_Subs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size);
1670 
1671 extern ir_op *op_ia32_SwitchJmp;
1672 
1673 static inline bool is_ia32_SwitchJmp(ir_node const *const n)
1674 {
1675  return get_irn_op(n) == op_ia32_SwitchJmp;
1676 }
1677 
1681 ir_node *new_bd_ia32_SwitchJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, int n_res, const ir_switch_table *switch_table, const ir_entity *table_entity);
1682 
1683 extern ir_op *op_ia32_Test;
1684 
1685 static inline bool is_ia32_Test(ir_node const *const n)
1686 {
1687  return get_irn_op(n) == op_ia32_Test;
1688 }
1689 
1693 ir_node *new_bd_ia32_Test(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted);
1697 ir_node *new_bd_ia32_Test_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted);
1698 
1699 extern ir_op *op_ia32_UD2;
1700 
1701 static inline bool is_ia32_UD2(ir_node const *const n)
1702 {
1703  return get_irn_op(n) == op_ia32_UD2;
1704 }
1705 
1709 ir_node *new_bd_ia32_UD2(dbg_info *dbgi, ir_node *block, ir_node *mem);
1710 
1711 extern ir_op *op_ia32_Ucomis;
1712 
1713 static inline bool is_ia32_Ucomis(ir_node const *const n)
1714 {
1715  return get_irn_op(n) == op_ia32_Ucomis;
1716 }
1717 
1721 ir_node *new_bd_ia32_Ucomis(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted);
1722 
1723 extern ir_op *op_ia32_Xor;
1724 
1725 static inline bool is_ia32_Xor(ir_node const *const n)
1726 {
1727  return get_irn_op(n) == op_ia32_Xor;
1728 }
1729 
1733 ir_node *new_bd_ia32_Xor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
1737 ir_node *new_bd_ia32_Xor_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
1738 
1739 extern ir_op *op_ia32_Xor0;
1740 
1741 static inline bool is_ia32_Xor0(ir_node const *const n)
1742 {
1743  return get_irn_op(n) == op_ia32_Xor0;
1744 }
1745 
1749 ir_node *new_bd_ia32_Xor0(dbg_info *dbgi, ir_node *block, x86_insn_size_t size);
1750 
1751 extern ir_op *op_ia32_XorHighLow;
1752 
1753 static inline bool is_ia32_XorHighLow(ir_node const *const n)
1754 {
1755  return get_irn_op(n) == op_ia32_XorHighLow;
1756 }
1757 
1761 ir_node *new_bd_ia32_XorHighLow(dbg_info *dbgi, ir_node *block, ir_node *value);
1762 
1763 extern ir_op *op_ia32_XorMem;
1764 
1765 static inline bool is_ia32_XorMem(ir_node const *const n)
1766 {
1767  return get_irn_op(n) == op_ia32_XorMem;
1768 }
1769 
1773 ir_node *new_bd_ia32_XorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1777 ir_node *new_bd_ia32_XorMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1778 
1779 extern ir_op *op_ia32_Xorp;
1780 
1781 static inline bool is_ia32_Xorp(ir_node const *const n)
1782 {
1783  return get_irn_op(n) == op_ia32_Xorp;
1784 }
1785 
1789 ir_node *new_bd_ia32_Xorp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size);
1790 
1791 extern ir_op *op_ia32_emms;
1792 
1793 static inline bool is_ia32_emms(ir_node const *const n)
1794 {
1795  return get_irn_op(n) == op_ia32_emms;
1796 }
1797 
1801 ir_node *new_bd_ia32_emms(dbg_info *dbgi, ir_node *block);
1802 
1803 extern ir_op *op_ia32_fabs;
1804 
1805 static inline bool is_ia32_fabs(ir_node const *const n)
1806 {
1807  return get_irn_op(n) == op_ia32_fabs;
1808 }
1809 
1813 ir_node *new_bd_ia32_fabs(dbg_info *dbgi, ir_node *block, ir_node *value);
1814 
1815 extern ir_op *op_ia32_fadd;
1816 
1817 static inline bool is_ia32_fadd(ir_node const *const n)
1818 {
1819  return get_irn_op(n) == op_ia32_fadd;
1820 }
1821 
1825 ir_node *new_bd_ia32_fadd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size);
1826 
1827 extern ir_op *op_ia32_fchs;
1828 
1829 static inline bool is_ia32_fchs(ir_node const *const n)
1830 {
1831  return get_irn_op(n) == op_ia32_fchs;
1832 }
1833 
1837 ir_node *new_bd_ia32_fchs(dbg_info *dbgi, ir_node *block, ir_node *value);
1838 
1839 extern ir_op *op_ia32_fdiv;
1840 
1841 static inline bool is_ia32_fdiv(ir_node const *const n)
1842 {
1843  return get_irn_op(n) == op_ia32_fdiv;
1844 }
1845 
1849 ir_node *new_bd_ia32_fdiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size);
1850 
1851 extern ir_op *op_ia32_fdup;
1852 
1853 static inline bool is_ia32_fdup(ir_node const *const n)
1854 {
1855  return get_irn_op(n) == op_ia32_fdup;
1856 }
1857 
1861 ir_node *new_bd_ia32_fdup(dbg_info *dbgi, ir_node *block, ir_node *val, const arch_register_t *reg);
1862 
1863 extern ir_op *op_ia32_femms;
1864 
1865 static inline bool is_ia32_femms(ir_node const *const n)
1866 {
1867  return get_irn_op(n) == op_ia32_femms;
1868 }
1869 
1873 ir_node *new_bd_ia32_femms(dbg_info *dbgi, ir_node *block);
1874 
1875 extern ir_op *op_ia32_ffreep;
1876 
1877 static inline bool is_ia32_ffreep(ir_node const *const n)
1878 {
1879  return get_irn_op(n) == op_ia32_ffreep;
1880 }
1881 
1885 ir_node *new_bd_ia32_ffreep(dbg_info *dbgi, ir_node *block, const arch_register_t *reg);
1886 
1887 extern ir_op *op_ia32_fild;
1888 
1889 static inline bool is_ia32_fild(ir_node const *const n)
1890 {
1891  return get_irn_op(n) == op_ia32_fild;
1892 }
1893 
1897 ir_node *new_bd_ia32_fild(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size);
1898 
1899 extern ir_op *op_ia32_fist;
1900 
1901 static inline bool is_ia32_fist(ir_node const *const n)
1902 {
1903  return get_irn_op(n) == op_ia32_fist;
1904 }
1905 
1909 ir_node *new_bd_ia32_fist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw, x86_insn_size_t size);
1910 
1911 extern ir_op *op_ia32_fistp;
1912 
1913 static inline bool is_ia32_fistp(ir_node const *const n)
1914 {
1915  return get_irn_op(n) == op_ia32_fistp;
1916 }
1917 
1921 ir_node *new_bd_ia32_fistp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw, x86_insn_size_t size);
1922 
1923 extern ir_op *op_ia32_fisttp;
1924 
1925 static inline bool is_ia32_fisttp(ir_node const *const n)
1926 {
1927  return get_irn_op(n) == op_ia32_fisttp;
1928 }
1929 
1933 ir_node *new_bd_ia32_fisttp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
1934 
1935 extern ir_op *op_ia32_fld;
1936 
1937 static inline bool is_ia32_fld(ir_node const *const n)
1938 {
1939  return get_irn_op(n) == op_ia32_fld;
1940 }
1941 
1945 ir_node *new_bd_ia32_fld(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size);
1946 
1947 extern ir_op *op_ia32_fld1;
1948 
1949 static inline bool is_ia32_fld1(ir_node const *const n)
1950 {
1951  return get_irn_op(n) == op_ia32_fld1;
1952 }
1953 
1957 ir_node *new_bd_ia32_fld1(dbg_info *dbgi, ir_node *block);
1958 
1959 extern ir_op *op_ia32_fldl2e;
1960 
1961 static inline bool is_ia32_fldl2e(ir_node const *const n)
1962 {
1963  return get_irn_op(n) == op_ia32_fldl2e;
1964 }
1965 
1969 ir_node *new_bd_ia32_fldl2e(dbg_info *dbgi, ir_node *block);
1970 
1971 extern ir_op *op_ia32_fldl2t;
1972 
1973 static inline bool is_ia32_fldl2t(ir_node const *const n)
1974 {
1975  return get_irn_op(n) == op_ia32_fldl2t;
1976 }
1977 
1981 ir_node *new_bd_ia32_fldl2t(dbg_info *dbgi, ir_node *block);
1982 
1983 extern ir_op *op_ia32_fldlg2;
1984 
1985 static inline bool is_ia32_fldlg2(ir_node const *const n)
1986 {
1987  return get_irn_op(n) == op_ia32_fldlg2;
1988 }
1989 
1993 ir_node *new_bd_ia32_fldlg2(dbg_info *dbgi, ir_node *block);
1994 
1995 extern ir_op *op_ia32_fldln2;
1996 
1997 static inline bool is_ia32_fldln2(ir_node const *const n)
1998 {
1999  return get_irn_op(n) == op_ia32_fldln2;
2000 }
2001 
2005 ir_node *new_bd_ia32_fldln2(dbg_info *dbgi, ir_node *block);
2006 
2007 extern ir_op *op_ia32_fldpi;
2008 
2009 static inline bool is_ia32_fldpi(ir_node const *const n)
2010 {
2011  return get_irn_op(n) == op_ia32_fldpi;
2012 }
2013 
2017 ir_node *new_bd_ia32_fldpi(dbg_info *dbgi, ir_node *block);
2018 
2019 extern ir_op *op_ia32_fldz;
2020 
2021 static inline bool is_ia32_fldz(ir_node const *const n)
2022 {
2023  return get_irn_op(n) == op_ia32_fldz;
2024 }
2025 
2029 ir_node *new_bd_ia32_fldz(dbg_info *dbgi, ir_node *block);
2030 
2031 extern ir_op *op_ia32_fmul;
2032 
2033 static inline bool is_ia32_fmul(ir_node const *const n)
2034 {
2035  return get_irn_op(n) == op_ia32_fmul;
2036 }
2037 
2041 ir_node *new_bd_ia32_fmul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size);
2042 
2043 extern ir_op *op_ia32_fpop;
2044 
2045 static inline bool is_ia32_fpop(ir_node const *const n)
2046 {
2047  return get_irn_op(n) == op_ia32_fpop;
2048 }
2049 
2053 ir_node *new_bd_ia32_fpop(dbg_info *dbgi, ir_node *block, const arch_register_t *reg);
2054 
2055 extern ir_op *op_ia32_fst;
2056 
2057 static inline bool is_ia32_fst(ir_node const *const n)
2058 {
2059  return get_irn_op(n) == op_ia32_fst;
2060 }
2061 
2065 ir_node *new_bd_ia32_fst(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
2066 
2067 extern ir_op *op_ia32_fstp;
2068 
2069 static inline bool is_ia32_fstp(ir_node const *const n)
2070 {
2071  return get_irn_op(n) == op_ia32_fstp;
2072 }
2073 
2077 ir_node *new_bd_ia32_fstp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
2078 
2079 extern ir_op *op_ia32_fsub;
2080 
2081 static inline bool is_ia32_fsub(ir_node const *const n)
2082 {
2083  return get_irn_op(n) == op_ia32_fsub;
2084 }
2085 
2089 ir_node *new_bd_ia32_fsub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size);
2090 
2091 extern ir_op *op_ia32_fxch;
2092 
2093 static inline bool is_ia32_fxch(ir_node const *const n)
2094 {
2095  return get_irn_op(n) == op_ia32_fxch;
2096 }
2097 
2101 ir_node *new_bd_ia32_fxch(dbg_info *dbgi, ir_node *block, const arch_register_t *reg);
2102 
2103 extern ir_op *op_ia32_l_Adc;
2104 
2105 static inline bool is_ia32_l_Adc(ir_node const *const n)
2106 {
2107  return get_irn_op(n) == op_ia32_l_Adc;
2108 }
2109 
2113 ir_node *new_bd_ia32_l_Adc(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *eflags, ir_mode *mode);
2114 
2115 extern ir_op *op_ia32_l_Add;
2116 
2117 static inline bool is_ia32_l_Add(ir_node const *const n)
2118 {
2119  return get_irn_op(n) == op_ia32_l_Add;
2120 }
2121 
2125 ir_node *new_bd_ia32_l_Add(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right);
2126 
2127 extern ir_op *op_ia32_l_FloattoLL;
2128 
2129 static inline bool is_ia32_l_FloattoLL(ir_node const *const n)
2130 {
2131  return get_irn_op(n) == op_ia32_l_FloattoLL;
2132 }
2133 
2137 ir_node *new_bd_ia32_l_FloattoLL(dbg_info *dbgi, ir_node *block, ir_node *val);
2138 
2139 extern ir_op *op_ia32_l_IMul;
2140 
2141 static inline bool is_ia32_l_IMul(ir_node const *const n)
2142 {
2143  return get_irn_op(n) == op_ia32_l_IMul;
2144 }
2145 
2149 ir_node *new_bd_ia32_l_IMul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right);
2150 
2151 extern ir_op *op_ia32_l_LLtoFloat;
2152 
2153 static inline bool is_ia32_l_LLtoFloat(ir_node const *const n)
2154 {
2155  return get_irn_op(n) == op_ia32_l_LLtoFloat;
2156 }
2157 
2161 ir_node *new_bd_ia32_l_LLtoFloat(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_mode *mode);
2162 
2163 extern ir_op *op_ia32_l_Minus64;
2164 
2165 static inline bool is_ia32_l_Minus64(ir_node const *const n)
2166 {
2167  return get_irn_op(n) == op_ia32_l_Minus64;
2168 }
2169 
2173 ir_node *new_bd_ia32_l_Minus64(dbg_info *dbgi, ir_node *block, ir_node *low, ir_node *high);
2174 
2175 extern ir_op *op_ia32_l_Mul;
2176 
2177 static inline bool is_ia32_l_Mul(ir_node const *const n)
2178 {
2179  return get_irn_op(n) == op_ia32_l_Mul;
2180 }
2181 
2185 ir_node *new_bd_ia32_l_Mul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right);
2186 
2187 extern ir_op *op_ia32_l_Sbb;
2188 
2189 static inline bool is_ia32_l_Sbb(ir_node const *const n)
2190 {
2191  return get_irn_op(n) == op_ia32_l_Sbb;
2192 }
2193 
2197 ir_node *new_bd_ia32_l_Sbb(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, ir_mode *mode);
2198 
2199 extern ir_op *op_ia32_l_Sub;
2200 
2201 static inline bool is_ia32_l_Sub(ir_node const *const n)
2202 {
2203  return get_irn_op(n) == op_ia32_l_Sub;
2204 }
2205 
2209 ir_node *new_bd_ia32_l_Sub(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend);
2210 
2211 extern ir_op *op_ia32_xAllOnes;
2212 
2213 static inline bool is_ia32_xAllOnes(ir_node const *const n)
2214 {
2215  return get_irn_op(n) == op_ia32_xAllOnes;
2216 }
2217 
2221 ir_node *new_bd_ia32_xAllOnes(dbg_info *dbgi, ir_node *block, x86_insn_size_t size);
2222 
2223 extern ir_op *op_ia32_xLoad;
2224 
2225 static inline bool is_ia32_xLoad(ir_node const *const n)
2226 {
2227  return get_irn_op(n) == op_ia32_xLoad;
2228 }
2229 
2233 ir_node *new_bd_ia32_xLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size);
2234 
2235 extern ir_op *op_ia32_xPzero;
2236 
2237 static inline bool is_ia32_xPzero(ir_node const *const n)
2238 {
2239  return get_irn_op(n) == op_ia32_xPzero;
2240 }
2241 
2245 ir_node *new_bd_ia32_xPzero(dbg_info *dbgi, ir_node *block, x86_insn_size_t size);
2246 
2247 extern ir_op *op_ia32_xStore;
2248 
2249 static inline bool is_ia32_xStore(ir_node const *const n)
2250 {
2251  return get_irn_op(n) == op_ia32_xStore;
2252 }
2253 
2257 ir_node *new_bd_ia32_xStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
2258 
2259 extern ir_op *op_ia32_xZero;
2260 
2261 static inline bool is_ia32_xZero(ir_node const *const n)
2262 {
2263  return get_irn_op(n) == op_ia32_xZero;
2264 }
2265 
2269 ir_node *new_bd_ia32_xZero(dbg_info *dbgi, ir_node *block, x86_insn_size_t size);
2270 
2271 extern ir_op *op_ia32_xxLoad;
2272 
2273 static inline bool is_ia32_xxLoad(ir_node const *const n)
2274 {
2275  return get_irn_op(n) == op_ia32_xxLoad;
2276 }
2277 
2281 ir_node *new_bd_ia32_xxLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size);
2282 
2283 extern ir_op *op_ia32_xxStore;
2284 
2285 static inline bool is_ia32_xxStore(ir_node const *const n)
2286 {
2287  return get_irn_op(n) == op_ia32_xxStore;
2288 }
2289 
2293 ir_node *new_bd_ia32_xxStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size);
2294 
2295 
2296 typedef enum pn_ia32_Adc {
2297  pn_ia32_Adc_res = 0,
2298  pn_ia32_Adc_flags = 1,
2299  pn_ia32_Adc_M = 2,
2300 } pn_ia32_Adc;
2301 
2302 typedef enum n_ia32_Adc {
2303  n_ia32_Adc_base = 0,
2304  n_ia32_Adc_index = 1,
2305  n_ia32_Adc_mem = 2,
2306  n_ia32_Adc_left = 3,
2307  n_ia32_Adc_right = 4,
2308  n_ia32_Adc_eflags = 5,
2309 } n_ia32_Adc;
2310 
2311 typedef enum pn_ia32_Add {
2312  pn_ia32_Add_res = 0,
2313  pn_ia32_Add_flags = 1,
2314  pn_ia32_Add_M = 2,
2315 } pn_ia32_Add;
2316 
2317 typedef enum n_ia32_Add {
2318  n_ia32_Add_base = 0,
2319  n_ia32_Add_index = 1,
2320  n_ia32_Add_mem = 2,
2321  n_ia32_Add_left = 3,
2322  n_ia32_Add_right = 4,
2323 } n_ia32_Add;
2324 
2325 typedef enum pn_ia32_AddMem {
2326  pn_ia32_AddMem_unused = 0,
2327  pn_ia32_AddMem_flags = 1,
2328  pn_ia32_AddMem_M = 2,
2329 } pn_ia32_AddMem;
2330 
2331 typedef enum n_ia32_AddMem {
2332  n_ia32_AddMem_base = 0,
2333  n_ia32_AddMem_index = 1,
2334  n_ia32_AddMem_mem = 2,
2335  n_ia32_AddMem_val = 3,
2336 } n_ia32_AddMem;
2337 
2338 typedef enum pn_ia32_AddSP {
2339  pn_ia32_AddSP_stack = 0,
2340  pn_ia32_AddSP_M = 1,
2341 } pn_ia32_AddSP;
2342 
2343 typedef enum n_ia32_AddSP {
2344  n_ia32_AddSP_base = 0,
2345  n_ia32_AddSP_index = 1,
2346  n_ia32_AddSP_mem = 2,
2347  n_ia32_AddSP_stack = 3,
2348  n_ia32_AddSP_amount = 4,
2349 } n_ia32_AddSP;
2350 
2351 typedef enum pn_ia32_Adds {
2352  pn_ia32_Adds_res = 0,
2353  pn_ia32_Adds_flags = 1,
2354  pn_ia32_Adds_M = 2,
2355 } pn_ia32_Adds;
2356 
2357 typedef enum n_ia32_Adds {
2358  n_ia32_Adds_base = 0,
2359  n_ia32_Adds_index = 1,
2360  n_ia32_Adds_mem = 2,
2361  n_ia32_Adds_left = 3,
2362  n_ia32_Adds_right = 4,
2363 } n_ia32_Adds;
2364 
2365 typedef enum pn_ia32_And {
2366  pn_ia32_And_res = 0,
2367  pn_ia32_And_flags = 1,
2368  pn_ia32_And_M = 2,
2369 } pn_ia32_And;
2370 
2371 typedef enum n_ia32_And {
2372  n_ia32_And_base = 0,
2373  n_ia32_And_index = 1,
2374  n_ia32_And_mem = 2,
2375  n_ia32_And_left = 3,
2376  n_ia32_And_right = 4,
2377 } n_ia32_And;
2378 
2379 typedef enum pn_ia32_AndMem {
2380  pn_ia32_AndMem_unused = 0,
2381  pn_ia32_AndMem_flags = 1,
2382  pn_ia32_AndMem_M = 2,
2383 } pn_ia32_AndMem;
2384 
2385 typedef enum n_ia32_AndMem {
2386  n_ia32_AndMem_base = 0,
2387  n_ia32_AndMem_index = 1,
2388  n_ia32_AndMem_mem = 2,
2389  n_ia32_AndMem_val = 3,
2390 } n_ia32_AndMem;
2391 
2392 typedef enum pn_ia32_Andnp {
2393  pn_ia32_Andnp_res = 0,
2394  pn_ia32_Andnp_flags = 1,
2395  pn_ia32_Andnp_M = 2,
2396 } pn_ia32_Andnp;
2397 
2398 typedef enum n_ia32_Andnp {
2399  n_ia32_Andnp_base = 0,
2400  n_ia32_Andnp_index = 1,
2401  n_ia32_Andnp_mem = 2,
2402  n_ia32_Andnp_left = 3,
2403  n_ia32_Andnp_right = 4,
2404 } n_ia32_Andnp;
2405 
2406 typedef enum pn_ia32_Andp {
2407  pn_ia32_Andp_res = 0,
2408  pn_ia32_Andp_flags = 1,
2409  pn_ia32_Andp_M = 2,
2410 } pn_ia32_Andp;
2411 
2412 typedef enum n_ia32_Andp {
2413  n_ia32_Andp_base = 0,
2414  n_ia32_Andp_index = 1,
2415  n_ia32_Andp_mem = 2,
2416  n_ia32_Andp_left = 3,
2417  n_ia32_Andp_right = 4,
2418 } n_ia32_Andp;
2419 
2420 typedef enum n_ia32_Breakpoint {
2421  n_ia32_Breakpoint_mem = 0,
2422 } n_ia32_Breakpoint;
2423 
2424 typedef enum pn_ia32_Bsf {
2425  pn_ia32_Bsf_res = 0,
2426  pn_ia32_Bsf_flags = 1,
2427  pn_ia32_Bsf_M = 2,
2428 } pn_ia32_Bsf;
2429 
2430 typedef enum n_ia32_Bsf {
2431  n_ia32_Bsf_base = 0,
2432  n_ia32_Bsf_index = 1,
2433  n_ia32_Bsf_mem = 2,
2434  n_ia32_Bsf_operand = 3,
2435 } n_ia32_Bsf;
2436 
2437 typedef enum pn_ia32_Bsr {
2438  pn_ia32_Bsr_res = 0,
2439  pn_ia32_Bsr_flags = 1,
2440  pn_ia32_Bsr_M = 2,
2441 } pn_ia32_Bsr;
2442 
2443 typedef enum n_ia32_Bsr {
2444  n_ia32_Bsr_base = 0,
2445  n_ia32_Bsr_index = 1,
2446  n_ia32_Bsr_mem = 2,
2447  n_ia32_Bsr_operand = 3,
2448 } n_ia32_Bsr;
2449 
2450 typedef enum pn_ia32_Bswap {
2451  pn_ia32_Bswap_res = 0,
2452 } pn_ia32_Bswap;
2453 
2454 typedef enum n_ia32_Bswap {
2455  n_ia32_Bswap_val = 0,
2456 } n_ia32_Bswap;
2457 
2458 typedef enum pn_ia32_Bswap16 {
2459  pn_ia32_Bswap16_res = 0,
2460 } pn_ia32_Bswap16;
2461 
2462 typedef enum n_ia32_Bswap16 {
2463  n_ia32_Bswap16_val = 0,
2464 } n_ia32_Bswap16;
2465 
2466 typedef enum n_ia32_Bt {
2467  n_ia32_Bt_left = 0,
2468  n_ia32_Bt_right = 1,
2469 } n_ia32_Bt;
2470 
2471 typedef enum pn_ia32_CMovcc {
2472  pn_ia32_CMovcc_res = 0,
2473  pn_ia32_CMovcc_unused = 1,
2474  pn_ia32_CMovcc_M = 2,
2475 } pn_ia32_CMovcc;
2476 
2477 typedef enum n_ia32_CMovcc {
2478  n_ia32_CMovcc_base = 0,
2479  n_ia32_CMovcc_index = 1,
2480  n_ia32_CMovcc_mem = 2,
2481  n_ia32_CMovcc_val_false = 3,
2482  n_ia32_CMovcc_val_true = 4,
2483  n_ia32_CMovcc_eflags = 5,
2484 } n_ia32_CMovcc;
2485 
2486 typedef enum pn_ia32_Call {
2487  pn_ia32_Call_mem = 0,
2488  pn_ia32_Call_stack = 1,
2489  pn_ia32_Call_first_result = 2,
2490 } pn_ia32_Call;
2491 
2492 typedef enum n_ia32_Call {
2493  n_ia32_Call_base = 0,
2494  n_ia32_Call_index = 1,
2495  n_ia32_Call_mem = 2,
2496  n_ia32_Call_callee = 3,
2497  n_ia32_Call_stack = 4,
2498  n_ia32_Call_first_argument = 5,
2499 } n_ia32_Call;
2500 
2501 typedef enum n_ia32_Cltd {
2502  n_ia32_Cltd_val = 0,
2503 } n_ia32_Cltd;
2504 
2505 typedef enum pn_ia32_Cmp {
2506  pn_ia32_Cmp_eflags = 0,
2507  pn_ia32_Cmp_unused = 1,
2508  pn_ia32_Cmp_M = 2,
2509 } pn_ia32_Cmp;
2510 
2511 typedef enum n_ia32_Cmp {
2512  n_ia32_Cmp_base = 0,
2513  n_ia32_Cmp_index = 1,
2514  n_ia32_Cmp_mem = 2,
2515  n_ia32_Cmp_left = 3,
2516  n_ia32_Cmp_right = 4,
2517 } n_ia32_Cmp;
2518 
2519 typedef enum pn_ia32_CmpXChgMem {
2520  pn_ia32_CmpXChgMem_res = 0,
2521  pn_ia32_CmpXChgMem_flags = 1,
2522  pn_ia32_CmpXChgMem_M = 2,
2523 } pn_ia32_CmpXChgMem;
2524 
2525 typedef enum n_ia32_CmpXChgMem {
2526  n_ia32_CmpXChgMem_base = 0,
2527  n_ia32_CmpXChgMem_index = 1,
2528  n_ia32_CmpXChgMem_mem = 2,
2529  n_ia32_CmpXChgMem_old = 3,
2530  n_ia32_CmpXChgMem_new = 4,
2531 } n_ia32_CmpXChgMem;
2532 
2533 typedef enum pn_ia32_Const {
2534  pn_ia32_Const_res = 0,
2535 } pn_ia32_Const;
2536 
2537 typedef enum n_ia32_Conv_FP2FP {
2538  n_ia32_Conv_FP2FP_base = 0,
2539  n_ia32_Conv_FP2FP_index = 1,
2540  n_ia32_Conv_FP2FP_mem = 2,
2541  n_ia32_Conv_FP2FP_val = 3,
2542 } n_ia32_Conv_FP2FP;
2543 
2544 typedef enum n_ia32_Conv_FP2I {
2545  n_ia32_Conv_FP2I_base = 0,
2546  n_ia32_Conv_FP2I_index = 1,
2547  n_ia32_Conv_FP2I_mem = 2,
2548  n_ia32_Conv_FP2I_val = 3,
2549 } n_ia32_Conv_FP2I;
2550 
2551 typedef enum n_ia32_Conv_I2FP {
2552  n_ia32_Conv_I2FP_base = 0,
2553  n_ia32_Conv_I2FP_index = 1,
2554  n_ia32_Conv_I2FP_mem = 2,
2555  n_ia32_Conv_I2FP_val = 3,
2556 } n_ia32_Conv_I2FP;
2557 
2558 typedef enum pn_ia32_Conv_I2I {
2559  pn_ia32_Conv_I2I_res = 0,
2560  pn_ia32_Conv_I2I_unused = 1,
2561  pn_ia32_Conv_I2I_M = 2,
2562  pn_ia32_Conv_I2I_X_regular = 3,
2563  pn_ia32_Conv_I2I_X_except = 4,
2564 } pn_ia32_Conv_I2I;
2565 
2566 typedef enum n_ia32_Conv_I2I {
2567  n_ia32_Conv_I2I_base = 0,
2568  n_ia32_Conv_I2I_index = 1,
2569  n_ia32_Conv_I2I_mem = 2,
2570  n_ia32_Conv_I2I_val = 3,
2571 } n_ia32_Conv_I2I;
2572 
2573 typedef enum pn_ia32_CopyB {
2574  pn_ia32_CopyB_dest = 0,
2575  pn_ia32_CopyB_source = 1,
2576  pn_ia32_CopyB_count = 2,
2577  pn_ia32_CopyB_M = 3,
2578 } pn_ia32_CopyB;
2579 
2580 typedef enum n_ia32_CopyB {
2581  n_ia32_CopyB_dest = 0,
2582  n_ia32_CopyB_source = 1,
2583  n_ia32_CopyB_count = 2,
2584  n_ia32_CopyB_mem = 3,
2585 } n_ia32_CopyB;
2586 
2587 typedef enum pn_ia32_CopyB_i {
2588  pn_ia32_CopyB_i_dest = 0,
2589  pn_ia32_CopyB_i_source = 1,
2590  pn_ia32_CopyB_i_M = 2,
2591 } pn_ia32_CopyB_i;
2592 
2593 typedef enum n_ia32_CopyB_i {
2594  n_ia32_CopyB_i_dest = 0,
2595  n_ia32_CopyB_i_source = 1,
2596  n_ia32_CopyB_i_mem = 2,
2597 } n_ia32_CopyB_i;
2598 
2599 typedef enum pn_ia32_CopyEbpEsp {
2600  pn_ia32_CopyEbpEsp_esp = 0,
2601 } pn_ia32_CopyEbpEsp;
2602 
2603 typedef enum n_ia32_CopyEbpEsp {
2604  n_ia32_CopyEbpEsp_ebp = 0,
2605 } n_ia32_CopyEbpEsp;
2606 
2607 typedef enum n_ia32_CvtSI2SD {
2608  n_ia32_CvtSI2SD_base = 0,
2609  n_ia32_CvtSI2SD_index = 1,
2610  n_ia32_CvtSI2SD_mem = 2,
2611  n_ia32_CvtSI2SD_val = 3,
2612 } n_ia32_CvtSI2SD;
2613 
2614 typedef enum n_ia32_CvtSI2SS {
2615  n_ia32_CvtSI2SS_base = 0,
2616  n_ia32_CvtSI2SS_index = 1,
2617  n_ia32_CvtSI2SS_mem = 2,
2618  n_ia32_CvtSI2SS_val = 3,
2619 } n_ia32_CvtSI2SS;
2620 
2621 typedef enum pn_ia32_Cwtl {
2622  pn_ia32_Cwtl_res = 0,
2623 } pn_ia32_Cwtl;
2624 
2625 typedef enum n_ia32_Cwtl {
2626  n_ia32_Cwtl_val = 0,
2627 } n_ia32_Cwtl;
2628 
2629 typedef enum pn_ia32_Dec {
2630  pn_ia32_Dec_res = 0,
2631  pn_ia32_Dec_flags = 1,
2632 } pn_ia32_Dec;
2633 
2634 typedef enum n_ia32_Dec {
2635  n_ia32_Dec_val = 0,
2636 } n_ia32_Dec;
2637 
2638 typedef enum pn_ia32_DecMem {
2639  pn_ia32_DecMem_unused = 0,
2640  pn_ia32_DecMem_flags = 1,
2641  pn_ia32_DecMem_M = 2,
2642 } pn_ia32_DecMem;
2643 
2644 typedef enum n_ia32_DecMem {
2645  n_ia32_DecMem_base = 0,
2646  n_ia32_DecMem_index = 1,
2647  n_ia32_DecMem_mem = 2,
2648 } n_ia32_DecMem;
2649 
2650 typedef enum pn_ia32_Div {
2651  pn_ia32_Div_div_res = 0,
2652  pn_ia32_Div_flags = 1,
2653  pn_ia32_Div_M = 2,
2654  pn_ia32_Div_mod_res = 3,
2655  pn_ia32_Div_X_regular = 4,
2656  pn_ia32_Div_X_except = 5,
2657 } pn_ia32_Div;
2658 
2659 typedef enum n_ia32_Div {
2660  n_ia32_Div_base = 0,
2661  n_ia32_Div_index = 1,
2662  n_ia32_Div_mem = 2,
2663  n_ia32_Div_divisor = 3,
2664  n_ia32_Div_dividend_low = 4,
2665  n_ia32_Div_dividend_high = 5,
2666 } n_ia32_Div;
2667 
2668 typedef enum pn_ia32_Divs {
2669  pn_ia32_Divs_res = 0,
2670  pn_ia32_Divs_flags = 1,
2671  pn_ia32_Divs_M = 2,
2672 } pn_ia32_Divs;
2673 
2674 typedef enum n_ia32_Divs {
2675  n_ia32_Divs_base = 0,
2676  n_ia32_Divs_index = 1,
2677  n_ia32_Divs_mem = 2,
2678  n_ia32_Divs_left = 3,
2679  n_ia32_Divs_right = 4,
2680 } n_ia32_Divs;
2681 
2682 typedef enum pn_ia32_Enter {
2683  pn_ia32_Enter_frame = 0,
2684  pn_ia32_Enter_stack = 1,
2685  pn_ia32_Enter_M = 2,
2686 } pn_ia32_Enter;
2687 
2688 typedef enum n_ia32_FldCW {
2689  n_ia32_FldCW_base = 0,
2690  n_ia32_FldCW_index = 1,
2691  n_ia32_FldCW_mem = 2,
2692 } n_ia32_FldCW;
2693 
2694 typedef enum n_ia32_FnstCW {
2695  n_ia32_FnstCW_base = 0,
2696  n_ia32_FnstCW_index = 1,
2697  n_ia32_FnstCW_mem = 2,
2698  n_ia32_FnstCW_fpcw = 3,
2699 } n_ia32_FnstCW;
2700 
2701 typedef enum n_ia32_FnstCWNOP {
2702  n_ia32_FnstCWNOP_fpcw = 0,
2703 } n_ia32_FnstCWNOP;
2704 
2705 typedef enum pn_ia32_FtstFnstsw {
2706  pn_ia32_FtstFnstsw_flags = 0,
2707 } pn_ia32_FtstFnstsw;
2708 
2709 typedef enum n_ia32_FtstFnstsw {
2710  n_ia32_FtstFnstsw_left = 0,
2711 } n_ia32_FtstFnstsw;
2712 
2713 typedef enum pn_ia32_FucomFnstsw {
2714  pn_ia32_FucomFnstsw_flags = 0,
2715 } pn_ia32_FucomFnstsw;
2716 
2717 typedef enum n_ia32_FucomFnstsw {
2718  n_ia32_FucomFnstsw_left = 0,
2719  n_ia32_FucomFnstsw_right = 1,
2720 } n_ia32_FucomFnstsw;
2721 
2722 typedef enum pn_ia32_Fucomi {
2723  pn_ia32_Fucomi_flags = 0,
2724 } pn_ia32_Fucomi;
2725 
2726 typedef enum n_ia32_Fucomi {
2727  n_ia32_Fucomi_left = 0,
2728  n_ia32_Fucomi_right = 1,
2729 } n_ia32_Fucomi;
2730 
2731 typedef enum pn_ia32_FucomppFnstsw {
2732  pn_ia32_FucomppFnstsw_flags = 0,
2733 } pn_ia32_FucomppFnstsw;
2734 
2735 typedef enum n_ia32_FucomppFnstsw {
2736  n_ia32_FucomppFnstsw_left = 0,
2737  n_ia32_FucomppFnstsw_right = 1,
2738 } n_ia32_FucomppFnstsw;
2739 
2740 typedef enum pn_ia32_GetEIP {
2741  pn_ia32_GetEIP_res = 0,
2742 } pn_ia32_GetEIP;
2743 
2744 typedef enum pn_ia32_IDiv {
2745  pn_ia32_IDiv_div_res = 0,
2746  pn_ia32_IDiv_flags = 1,
2747  pn_ia32_IDiv_M = 2,
2748  pn_ia32_IDiv_mod_res = 3,
2749  pn_ia32_IDiv_X_regular = 4,
2750  pn_ia32_IDiv_X_except = 5,
2751 } pn_ia32_IDiv;
2752 
2753 typedef enum n_ia32_IDiv {
2754  n_ia32_IDiv_base = 0,
2755  n_ia32_IDiv_index = 1,
2756  n_ia32_IDiv_mem = 2,
2757  n_ia32_IDiv_divisor = 3,
2758  n_ia32_IDiv_dividend_low = 4,
2759  n_ia32_IDiv_dividend_high = 5,
2760 } n_ia32_IDiv;
2761 
2762 typedef enum pn_ia32_IJmp {
2763  pn_ia32_IJmp_jmp = 0,
2764  pn_ia32_IJmp_none = 1,
2765  pn_ia32_IJmp_M = 2,
2766 } pn_ia32_IJmp;
2767 
2768 typedef enum n_ia32_IJmp {
2769  n_ia32_IJmp_base = 0,
2770  n_ia32_IJmp_index = 1,
2771  n_ia32_IJmp_mem = 2,
2772  n_ia32_IJmp_target = 3,
2773 } n_ia32_IJmp;
2774 
2775 typedef enum pn_ia32_IMul {
2776  pn_ia32_IMul_res = 0,
2777  pn_ia32_IMul_flags = 1,
2778  pn_ia32_IMul_M = 2,
2779 } pn_ia32_IMul;
2780 
2781 typedef enum n_ia32_IMul {
2782  n_ia32_IMul_base = 0,
2783  n_ia32_IMul_index = 1,
2784  n_ia32_IMul_mem = 2,
2785  n_ia32_IMul_left = 3,
2786  n_ia32_IMul_right = 4,
2787 } n_ia32_IMul;
2788 
2789 typedef enum pn_ia32_IMul1OP {
2790  pn_ia32_IMul1OP_res_low = 0,
2791  pn_ia32_IMul1OP_flags = 1,
2792  pn_ia32_IMul1OP_M = 2,
2793  pn_ia32_IMul1OP_res_high = 3,
2794 } pn_ia32_IMul1OP;
2795 
2796 typedef enum n_ia32_IMul1OP {
2797  n_ia32_IMul1OP_base = 0,
2798  n_ia32_IMul1OP_index = 1,
2799  n_ia32_IMul1OP_mem = 2,
2800  n_ia32_IMul1OP_left = 3,
2801  n_ia32_IMul1OP_right = 4,
2802 } n_ia32_IMul1OP;
2803 
2804 typedef enum pn_ia32_IMulImm {
2805  pn_ia32_IMulImm_res = 0,
2806  pn_ia32_IMulImm_flags = 1,
2807  pn_ia32_IMulImm_M = 2,
2808 } pn_ia32_IMulImm;
2809 
2810 typedef enum n_ia32_IMulImm {
2811  n_ia32_IMulImm_base = 0,
2812  n_ia32_IMulImm_index = 1,
2813  n_ia32_IMulImm_mem = 2,
2814  n_ia32_IMulImm_left = 3,
2815  n_ia32_IMulImm_right = 4,
2816 } n_ia32_IMulImm;
2817 
2818 typedef enum pn_ia32_Inc {
2819  pn_ia32_Inc_res = 0,
2820  pn_ia32_Inc_flags = 1,
2821 } pn_ia32_Inc;
2822 
2823 typedef enum n_ia32_Inc {
2824  n_ia32_Inc_val = 0,
2825 } n_ia32_Inc;
2826 
2827 typedef enum pn_ia32_IncMem {
2828  pn_ia32_IncMem_unused = 0,
2829  pn_ia32_IncMem_flags = 1,
2830  pn_ia32_IncMem_M = 2,
2831 } pn_ia32_IncMem;
2832 
2833 typedef enum n_ia32_IncMem {
2834  n_ia32_IncMem_base = 0,
2835  n_ia32_IncMem_index = 1,
2836  n_ia32_IncMem_mem = 2,
2837 } n_ia32_IncMem;
2838 
2839 typedef enum pn_ia32_Inport {
2840  pn_ia32_Inport_res = 0,
2841  pn_ia32_Inport_M = 1,
2842 } pn_ia32_Inport;
2843 
2844 typedef enum n_ia32_Inport {
2845  n_ia32_Inport_port = 0,
2846  n_ia32_Inport_mem = 1,
2847 } n_ia32_Inport;
2848 
2849 typedef enum pn_ia32_Jcc {
2850  pn_ia32_Jcc_false = 0,
2851  pn_ia32_Jcc_true = 1,
2852 } pn_ia32_Jcc;
2853 
2854 typedef enum n_ia32_Jcc {
2855  n_ia32_Jcc_eflags = 0,
2856 } n_ia32_Jcc;
2857 
2858 typedef enum pn_ia32_LdTls {
2859  pn_ia32_LdTls_res = 0,
2860 } pn_ia32_LdTls;
2861 
2862 typedef enum pn_ia32_Lea {
2863  pn_ia32_Lea_res = 0,
2864 } pn_ia32_Lea;
2865 
2866 typedef enum n_ia32_Lea {
2867  n_ia32_Lea_base = 0,
2868  n_ia32_Lea_index = 1,
2869 } n_ia32_Lea;
2870 
2871 typedef enum pn_ia32_Leave {
2872  pn_ia32_Leave_frame = 0,
2873  pn_ia32_Leave_M = 1,
2874  pn_ia32_Leave_stack = 2,
2875 } pn_ia32_Leave;
2876 
2877 typedef enum pn_ia32_Load {
2878  pn_ia32_Load_res = 0,
2879  pn_ia32_Load_unused = 1,
2880  pn_ia32_Load_M = 2,
2881  pn_ia32_Load_X_regular = 3,
2882  pn_ia32_Load_X_except = 4,
2883 } pn_ia32_Load;
2884 
2885 typedef enum n_ia32_Load {
2886  n_ia32_Load_base = 0,
2887  n_ia32_Load_index = 1,
2888  n_ia32_Load_mem = 2,
2889 } n_ia32_Load;
2890 
2891 typedef enum pn_ia32_Maxs {
2892  pn_ia32_Maxs_res = 0,
2893  pn_ia32_Maxs_flags = 1,
2894  pn_ia32_Maxs_M = 2,
2895 } pn_ia32_Maxs;
2896 
2897 typedef enum n_ia32_Maxs {
2898  n_ia32_Maxs_base = 0,
2899  n_ia32_Maxs_index = 1,
2900  n_ia32_Maxs_mem = 2,
2901  n_ia32_Maxs_left = 3,
2902  n_ia32_Maxs_right = 4,
2903 } n_ia32_Maxs;
2904 
2905 typedef enum pn_ia32_Mins {
2906  pn_ia32_Mins_res = 0,
2907  pn_ia32_Mins_flags = 1,
2908  pn_ia32_Mins_M = 2,
2909 } pn_ia32_Mins;
2910 
2911 typedef enum n_ia32_Mins {
2912  n_ia32_Mins_base = 0,
2913  n_ia32_Mins_index = 1,
2914  n_ia32_Mins_mem = 2,
2915  n_ia32_Mins_left = 3,
2916  n_ia32_Mins_right = 4,
2917 } n_ia32_Mins;
2918 
2919 typedef enum pn_ia32_Minus64 {
2920  pn_ia32_Minus64_res_low = 0,
2921  pn_ia32_Minus64_res_high = 1,
2922 } pn_ia32_Minus64;
2923 
2924 typedef enum n_ia32_Minus64 {
2925  n_ia32_Minus64_low = 0,
2926  n_ia32_Minus64_high = 1,
2927 } n_ia32_Minus64;
2928 
2929 typedef enum pn_ia32_Mul {
2930  pn_ia32_Mul_res_low = 0,
2931  pn_ia32_Mul_flags = 1,
2932  pn_ia32_Mul_M = 2,
2933  pn_ia32_Mul_res_high = 3,
2934 } pn_ia32_Mul;
2935 
2936 typedef enum n_ia32_Mul {
2937  n_ia32_Mul_base = 0,
2938  n_ia32_Mul_index = 1,
2939  n_ia32_Mul_mem = 2,
2940  n_ia32_Mul_left = 3,
2941  n_ia32_Mul_right = 4,
2942 } n_ia32_Mul;
2943 
2944 typedef enum pn_ia32_Muls {
2945  pn_ia32_Muls_res = 0,
2946  pn_ia32_Muls_flags = 1,
2947  pn_ia32_Muls_M = 2,
2948 } pn_ia32_Muls;
2949 
2950 typedef enum n_ia32_Muls {
2951  n_ia32_Muls_base = 0,
2952  n_ia32_Muls_index = 1,
2953  n_ia32_Muls_mem = 2,
2954  n_ia32_Muls_left = 3,
2955  n_ia32_Muls_right = 4,
2956 } n_ia32_Muls;
2957 
2958 typedef enum pn_ia32_Neg {
2959  pn_ia32_Neg_res = 0,
2960  pn_ia32_Neg_flags = 1,
2961 } pn_ia32_Neg;
2962 
2963 typedef enum n_ia32_Neg {
2964  n_ia32_Neg_val = 0,
2965 } n_ia32_Neg;
2966 
2967 typedef enum pn_ia32_NegMem {
2968  pn_ia32_NegMem_unused = 0,
2969  pn_ia32_NegMem_flags = 1,
2970  pn_ia32_NegMem_M = 2,
2971 } pn_ia32_NegMem;
2972 
2973 typedef enum n_ia32_NegMem {
2974  n_ia32_NegMem_base = 0,
2975  n_ia32_NegMem_index = 1,
2976  n_ia32_NegMem_mem = 2,
2977 } n_ia32_NegMem;
2978 
2979 typedef enum pn_ia32_Not {
2980  pn_ia32_Not_res = 0,
2981 } pn_ia32_Not;
2982 
2983 typedef enum n_ia32_Not {
2984  n_ia32_Not_val = 0,
2985 } n_ia32_Not;
2986 
2987 typedef enum pn_ia32_NotMem {
2988  pn_ia32_NotMem_unused0 = 0,
2989  pn_ia32_NotMem_unused1 = 1,
2990  pn_ia32_NotMem_M = 2,
2991 } pn_ia32_NotMem;
2992 
2993 typedef enum n_ia32_NotMem {
2994  n_ia32_NotMem_base = 0,
2995  n_ia32_NotMem_index = 1,
2996  n_ia32_NotMem_mem = 2,
2997 } n_ia32_NotMem;
2998 
2999 typedef enum pn_ia32_Or {
3000  pn_ia32_Or_res = 0,
3001  pn_ia32_Or_flags = 1,
3002  pn_ia32_Or_M = 2,
3003 } pn_ia32_Or;
3004 
3005 typedef enum n_ia32_Or {
3006  n_ia32_Or_base = 0,
3007  n_ia32_Or_index = 1,
3008  n_ia32_Or_mem = 2,
3009  n_ia32_Or_left = 3,
3010  n_ia32_Or_right = 4,
3011 } n_ia32_Or;
3012 
3013 typedef enum pn_ia32_OrMem {
3014  pn_ia32_OrMem_unused = 0,
3015  pn_ia32_OrMem_flags = 1,
3016  pn_ia32_OrMem_M = 2,
3017 } pn_ia32_OrMem;
3018 
3019 typedef enum n_ia32_OrMem {
3020  n_ia32_OrMem_base = 0,
3021  n_ia32_OrMem_index = 1,
3022  n_ia32_OrMem_mem = 2,
3023  n_ia32_OrMem_val = 3,
3024 } n_ia32_OrMem;
3025 
3026 typedef enum pn_ia32_Orp {
3027  pn_ia32_Orp_res = 0,
3028  pn_ia32_Orp_flags = 1,
3029  pn_ia32_Orp_M = 2,
3030 } pn_ia32_Orp;
3031 
3032 typedef enum n_ia32_Orp {
3033  n_ia32_Orp_base = 0,
3034  n_ia32_Orp_index = 1,
3035  n_ia32_Orp_mem = 2,
3036  n_ia32_Orp_left = 3,
3037  n_ia32_Orp_right = 4,
3038 } n_ia32_Orp;
3039 
3040 typedef enum n_ia32_Outport {
3041  n_ia32_Outport_port = 0,
3042  n_ia32_Outport_value = 1,
3043  n_ia32_Outport_mem = 2,
3044 } n_ia32_Outport;
3045 
3046 typedef enum pn_ia32_Pop {
3047  pn_ia32_Pop_res = 0,
3048  pn_ia32_Pop_unused = 1,
3049  pn_ia32_Pop_M = 2,
3050  pn_ia32_Pop_stack = 3,
3051 } pn_ia32_Pop;
3052 
3053 typedef enum n_ia32_Pop {
3054  n_ia32_Pop_mem = 0,
3055  n_ia32_Pop_stack = 1,
3056 } n_ia32_Pop;
3057 
3058 typedef enum pn_ia32_PopMem {
3059  pn_ia32_PopMem_unused0 = 0,
3060  pn_ia32_PopMem_unused1 = 1,
3061  pn_ia32_PopMem_M = 2,
3062  pn_ia32_PopMem_stack = 3,
3063 } pn_ia32_PopMem;
3064 
3065 typedef enum n_ia32_PopMem {
3066  n_ia32_PopMem_base = 0,
3067  n_ia32_PopMem_index = 1,
3068  n_ia32_PopMem_mem = 2,
3069  n_ia32_PopMem_stack = 3,
3070 } n_ia32_PopMem;
3071 
3072 typedef enum pn_ia32_Popcnt {
3073  pn_ia32_Popcnt_res = 0,
3074  pn_ia32_Popcnt_flags = 1,
3075  pn_ia32_Popcnt_M = 2,
3076 } pn_ia32_Popcnt;
3077 
3078 typedef enum n_ia32_Popcnt {
3079  n_ia32_Popcnt_base = 0,
3080  n_ia32_Popcnt_index = 1,
3081  n_ia32_Popcnt_mem = 2,
3082  n_ia32_Popcnt_operand = 3,
3083 } n_ia32_Popcnt;
3084 
3085 typedef enum pn_ia32_Prefetch {
3086  pn_ia32_Prefetch_M = 0,
3087 } pn_ia32_Prefetch;
3088 
3089 typedef enum n_ia32_Prefetch {
3090  n_ia32_Prefetch_base = 0,
3091  n_ia32_Prefetch_index = 1,
3092  n_ia32_Prefetch_mem = 2,
3093 } n_ia32_Prefetch;
3094 
3095 typedef enum pn_ia32_PrefetchNTA {
3096  pn_ia32_PrefetchNTA_M = 0,
3097 } pn_ia32_PrefetchNTA;
3098 
3099 typedef enum n_ia32_PrefetchNTA {
3100  n_ia32_PrefetchNTA_base = 0,
3101  n_ia32_PrefetchNTA_index = 1,
3102  n_ia32_PrefetchNTA_mem = 2,
3103 } n_ia32_PrefetchNTA;
3104 
3105 typedef enum pn_ia32_PrefetchT0 {
3106  pn_ia32_PrefetchT0_M = 0,
3107 } pn_ia32_PrefetchT0;
3108 
3109 typedef enum n_ia32_PrefetchT0 {
3110  n_ia32_PrefetchT0_base = 0,
3111  n_ia32_PrefetchT0_index = 1,
3112  n_ia32_PrefetchT0_mem = 2,
3113 } n_ia32_PrefetchT0;
3114 
3115 typedef enum pn_ia32_PrefetchT1 {
3116  pn_ia32_PrefetchT1_M = 0,
3117 } pn_ia32_PrefetchT1;
3118 
3119 typedef enum n_ia32_PrefetchT1 {
3120  n_ia32_PrefetchT1_base = 0,
3121  n_ia32_PrefetchT1_index = 1,
3122  n_ia32_PrefetchT1_mem = 2,
3123 } n_ia32_PrefetchT1;
3124 
3125 typedef enum pn_ia32_PrefetchT2 {
3126  pn_ia32_PrefetchT2_M = 0,
3127 } pn_ia32_PrefetchT2;
3128 
3129 typedef enum n_ia32_PrefetchT2 {
3130  n_ia32_PrefetchT2_base = 0,
3131  n_ia32_PrefetchT2_index = 1,
3132  n_ia32_PrefetchT2_mem = 2,
3133 } n_ia32_PrefetchT2;
3134 
3135 typedef enum pn_ia32_PrefetchW {
3136  pn_ia32_PrefetchW_M = 0,
3137 } pn_ia32_PrefetchW;
3138 
3139 typedef enum n_ia32_PrefetchW {
3140  n_ia32_PrefetchW_base = 0,
3141  n_ia32_PrefetchW_index = 1,
3142  n_ia32_PrefetchW_mem = 2,
3143 } n_ia32_PrefetchW;
3144 
3145 typedef enum pn_ia32_Push {
3146  pn_ia32_Push_M = 0,
3147  pn_ia32_Push_stack = 1,
3148 } pn_ia32_Push;
3149 
3150 typedef enum n_ia32_Push {
3151  n_ia32_Push_base = 0,
3152  n_ia32_Push_index = 1,
3153  n_ia32_Push_mem = 2,
3154  n_ia32_Push_val = 3,
3155  n_ia32_Push_stack = 4,
3156 } n_ia32_Push;
3157 
3158 typedef enum pn_ia32_PushEax {
3159  pn_ia32_PushEax_stack = 0,
3160 } pn_ia32_PushEax;
3161 
3162 typedef enum n_ia32_PushEax {
3163  n_ia32_PushEax_stack = 0,
3164 } n_ia32_PushEax;
3165 
3166 typedef enum n_ia32_Return {
3167  n_ia32_Return_mem = 0,
3168  n_ia32_Return_stack = 1,
3169  n_ia32_Return_first_result = 2,
3170 } n_ia32_Return;
3171 
3172 typedef enum pn_ia32_Rol {
3173  pn_ia32_Rol_res = 0,
3174  pn_ia32_Rol_flags = 1,
3175 } pn_ia32_Rol;
3176 
3177 typedef enum n_ia32_Rol {
3178  n_ia32_Rol_val = 0,
3179  n_ia32_Rol_count = 1,
3180 } n_ia32_Rol;
3181 
3182 typedef enum pn_ia32_RolMem {
3183  pn_ia32_RolMem_unused = 0,
3184  pn_ia32_RolMem_flags = 1,
3185  pn_ia32_RolMem_M = 2,
3186 } pn_ia32_RolMem;
3187 
3188 typedef enum n_ia32_RolMem {
3189  n_ia32_RolMem_base = 0,
3190  n_ia32_RolMem_index = 1,
3191  n_ia32_RolMem_mem = 2,
3192  n_ia32_RolMem_count = 3,
3193 } n_ia32_RolMem;
3194 
3195 typedef enum pn_ia32_Ror {
3196  pn_ia32_Ror_res = 0,
3197  pn_ia32_Ror_flags = 1,
3198 } pn_ia32_Ror;
3199 
3200 typedef enum n_ia32_Ror {
3201  n_ia32_Ror_val = 0,
3202  n_ia32_Ror_count = 1,
3203 } n_ia32_Ror;
3204 
3205 typedef enum pn_ia32_RorMem {
3206  pn_ia32_RorMem_unused = 0,
3207  pn_ia32_RorMem_flags = 1,
3208  pn_ia32_RorMem_M = 2,
3209 } pn_ia32_RorMem;
3210 
3211 typedef enum n_ia32_RorMem {
3212  n_ia32_RorMem_base = 0,
3213  n_ia32_RorMem_index = 1,
3214  n_ia32_RorMem_mem = 2,
3215  n_ia32_RorMem_count = 3,
3216 } n_ia32_RorMem;
3217 
3218 typedef enum pn_ia32_Sahf {
3219  pn_ia32_Sahf_flags = 0,
3220 } pn_ia32_Sahf;
3221 
3222 typedef enum n_ia32_Sahf {
3223  n_ia32_Sahf_val = 0,
3224 } n_ia32_Sahf;
3225 
3226 typedef enum pn_ia32_Sar {
3227  pn_ia32_Sar_res = 0,
3228  pn_ia32_Sar_flags = 1,
3229 } pn_ia32_Sar;
3230 
3231 typedef enum n_ia32_Sar {
3232  n_ia32_Sar_val = 0,
3233  n_ia32_Sar_count = 1,
3234 } n_ia32_Sar;
3235 
3236 typedef enum pn_ia32_SarMem {
3237  pn_ia32_SarMem_unused = 0,
3238  pn_ia32_SarMem_flags = 1,
3239  pn_ia32_SarMem_M = 2,
3240 } pn_ia32_SarMem;
3241 
3242 typedef enum n_ia32_SarMem {
3243  n_ia32_SarMem_base = 0,
3244  n_ia32_SarMem_index = 1,
3245  n_ia32_SarMem_mem = 2,
3246  n_ia32_SarMem_count = 3,
3247 } n_ia32_SarMem;
3248 
3249 typedef enum pn_ia32_Sbb {
3250  pn_ia32_Sbb_res = 0,
3251  pn_ia32_Sbb_flags = 1,
3252  pn_ia32_Sbb_M = 2,
3253 } pn_ia32_Sbb;
3254 
3255 typedef enum n_ia32_Sbb {
3256  n_ia32_Sbb_base = 0,
3257  n_ia32_Sbb_index = 1,
3258  n_ia32_Sbb_mem = 2,
3259  n_ia32_Sbb_minuend = 3,
3260  n_ia32_Sbb_subtrahend = 4,
3261  n_ia32_Sbb_eflags = 5,
3262 } n_ia32_Sbb;
3263 
3264 typedef enum pn_ia32_Sbb0 {
3265  pn_ia32_Sbb0_res = 0,
3266  pn_ia32_Sbb0_flags = 1,
3267 } pn_ia32_Sbb0;
3268 
3269 typedef enum pn_ia32_Setcc {
3270  pn_ia32_Setcc_res = 0,
3271 } pn_ia32_Setcc;
3272 
3273 typedef enum n_ia32_Setcc {
3274  n_ia32_Setcc_eflags = 0,
3275 } n_ia32_Setcc;
3276 
3277 typedef enum n_ia32_SetccMem {
3278  n_ia32_SetccMem_base = 0,
3279  n_ia32_SetccMem_index = 1,
3280  n_ia32_SetccMem_mem = 2,
3281  n_ia32_SetccMem_eflags = 3,
3282 } n_ia32_SetccMem;
3283 
3284 typedef enum pn_ia32_Shl {
3285  pn_ia32_Shl_res = 0,
3286  pn_ia32_Shl_flags = 1,
3287 } pn_ia32_Shl;
3288 
3289 typedef enum n_ia32_Shl {
3290  n_ia32_Shl_val = 0,
3291  n_ia32_Shl_count = 1,
3292 } n_ia32_Shl;
3293 
3294 typedef enum pn_ia32_ShlD {
3295  pn_ia32_ShlD_res = 0,
3296  pn_ia32_ShlD_flags = 1,
3297 } pn_ia32_ShlD;
3298 
3299 typedef enum n_ia32_ShlD {
3300  n_ia32_ShlD_val_high = 0,
3301  n_ia32_ShlD_val_low = 1,
3302  n_ia32_ShlD_count = 2,
3303 } n_ia32_ShlD;
3304 
3305 typedef enum pn_ia32_ShlMem {
3306  pn_ia32_ShlMem_unused = 0,
3307  pn_ia32_ShlMem_flags = 1,
3308  pn_ia32_ShlMem_M = 2,
3309 } pn_ia32_ShlMem;
3310 
3311 typedef enum n_ia32_ShlMem {
3312  n_ia32_ShlMem_base = 0,
3313  n_ia32_ShlMem_index = 1,
3314  n_ia32_ShlMem_mem = 2,
3315  n_ia32_ShlMem_count = 3,
3316 } n_ia32_ShlMem;
3317 
3318 typedef enum pn_ia32_Shr {
3319  pn_ia32_Shr_res = 0,
3320  pn_ia32_Shr_flags = 1,
3321 } pn_ia32_Shr;
3322 
3323 typedef enum n_ia32_Shr {
3324  n_ia32_Shr_val = 0,
3325  n_ia32_Shr_count = 1,
3326 } n_ia32_Shr;
3327 
3328 typedef enum pn_ia32_ShrD {
3329  pn_ia32_ShrD_res = 0,
3330  pn_ia32_ShrD_flags = 1,
3331 } pn_ia32_ShrD;
3332 
3333 typedef enum n_ia32_ShrD {
3334  n_ia32_ShrD_val_high = 0,
3335  n_ia32_ShrD_val_low = 1,
3336  n_ia32_ShrD_count = 2,
3337 } n_ia32_ShrD;
3338 
3339 typedef enum pn_ia32_ShrMem {
3340  pn_ia32_ShrMem_unused = 0,
3341  pn_ia32_ShrMem_flags = 1,
3342  pn_ia32_ShrMem_M = 2,
3343 } pn_ia32_ShrMem;
3344 
3345 typedef enum n_ia32_ShrMem {
3346  n_ia32_ShrMem_base = 0,
3347  n_ia32_ShrMem_index = 1,
3348  n_ia32_ShrMem_mem = 2,
3349  n_ia32_ShrMem_count = 3,
3350 } n_ia32_ShrMem;
3351 
3352 typedef enum pn_ia32_Store {
3353  pn_ia32_Store_M = 0,
3354  pn_ia32_Store_X_regular = 1,
3355  pn_ia32_Store_X_except = 2,
3356 } pn_ia32_Store;
3357 
3358 typedef enum n_ia32_Store {
3359  n_ia32_Store_base = 0,
3360  n_ia32_Store_index = 1,
3361  n_ia32_Store_mem = 2,
3362  n_ia32_Store_val = 3,
3363 } n_ia32_Store;
3364 
3365 typedef enum pn_ia32_Sub {
3366  pn_ia32_Sub_res = 0,
3367  pn_ia32_Sub_flags = 1,
3368  pn_ia32_Sub_M = 2,
3369 } pn_ia32_Sub;
3370 
3371 typedef enum n_ia32_Sub {
3372  n_ia32_Sub_base = 0,
3373  n_ia32_Sub_index = 1,
3374  n_ia32_Sub_mem = 2,
3375  n_ia32_Sub_minuend = 3,
3376  n_ia32_Sub_subtrahend = 4,
3377 } n_ia32_Sub;
3378 
3379 typedef enum pn_ia32_SubMem {
3380  pn_ia32_SubMem_unused = 0,
3381  pn_ia32_SubMem_flags = 1,
3382  pn_ia32_SubMem_M = 2,
3383 } pn_ia32_SubMem;
3384 
3385 typedef enum n_ia32_SubMem {
3386  n_ia32_SubMem_base = 0,
3387  n_ia32_SubMem_index = 1,
3388  n_ia32_SubMem_mem = 2,
3389  n_ia32_SubMem_val = 3,
3390 } n_ia32_SubMem;
3391 
3392 typedef enum pn_ia32_SubSP {
3393  pn_ia32_SubSP_stack = 0,
3394  pn_ia32_SubSP_addr = 1,
3395  pn_ia32_SubSP_M = 2,
3396 } pn_ia32_SubSP;
3397 
3398 typedef enum n_ia32_SubSP {
3399  n_ia32_SubSP_base = 0,
3400  n_ia32_SubSP_index = 1,
3401  n_ia32_SubSP_mem = 2,
3402  n_ia32_SubSP_stack = 3,
3403  n_ia32_SubSP_amount = 4,
3404 } n_ia32_SubSP;
3405 
3406 typedef enum pn_ia32_Subs {
3407  pn_ia32_Subs_res = 0,
3408  pn_ia32_Subs_flags = 1,
3409  pn_ia32_Subs_M = 2,
3410 } pn_ia32_Subs;
3411 
3412 typedef enum n_ia32_Subs {
3413  n_ia32_Subs_base = 0,
3414  n_ia32_Subs_index = 1,
3415  n_ia32_Subs_mem = 2,
3416  n_ia32_Subs_minuend = 3,
3417  n_ia32_Subs_subtrahend = 4,
3418 } n_ia32_Subs;
3419 
3420 typedef enum n_ia32_SwitchJmp {
3421  n_ia32_SwitchJmp_base = 0,
3422  n_ia32_SwitchJmp_index = 1,
3423 } n_ia32_SwitchJmp;
3424 
3425 typedef enum pn_ia32_Test {
3426  pn_ia32_Test_eflags = 0,
3427  pn_ia32_Test_unused = 1,
3428  pn_ia32_Test_M = 2,
3429 } pn_ia32_Test;
3430 
3431 typedef enum n_ia32_Test {
3432  n_ia32_Test_base = 0,
3433  n_ia32_Test_index = 1,
3434  n_ia32_Test_mem = 2,
3435  n_ia32_Test_left = 3,
3436  n_ia32_Test_right = 4,
3437 } n_ia32_Test;
3438 
3439 typedef enum n_ia32_UD2 {
3440  n_ia32_UD2_mem = 0,
3441 } n_ia32_UD2;
3442 
3443 typedef enum pn_ia32_Ucomis {
3444  pn_ia32_Ucomis_flags = 0,
3445 } pn_ia32_Ucomis;
3446 
3447 typedef enum n_ia32_Ucomis {
3448  n_ia32_Ucomis_base = 0,
3449  n_ia32_Ucomis_index = 1,
3450  n_ia32_Ucomis_mem = 2,
3451  n_ia32_Ucomis_left = 3,
3452  n_ia32_Ucomis_right = 4,
3453 } n_ia32_Ucomis;
3454 
3455 typedef enum pn_ia32_Xor {
3456  pn_ia32_Xor_res = 0,
3457  pn_ia32_Xor_flags = 1,
3458  pn_ia32_Xor_M = 2,
3459 } pn_ia32_Xor;
3460 
3461 typedef enum n_ia32_Xor {
3462  n_ia32_Xor_base = 0,
3463  n_ia32_Xor_index = 1,
3464  n_ia32_Xor_mem = 2,
3465  n_ia32_Xor_left = 3,
3466  n_ia32_Xor_right = 4,
3467 } n_ia32_Xor;
3468 
3469 typedef enum pn_ia32_Xor0 {
3470  pn_ia32_Xor0_res = 0,
3471  pn_ia32_Xor0_flags = 1,
3472 } pn_ia32_Xor0;
3473 
3474 typedef enum pn_ia32_XorHighLow {
3475  pn_ia32_XorHighLow_res = 0,
3476  pn_ia32_XorHighLow_flags = 1,
3477 } pn_ia32_XorHighLow;
3478 
3479 typedef enum n_ia32_XorHighLow {
3480  n_ia32_XorHighLow_value = 0,
3481 } n_ia32_XorHighLow;
3482 
3483 typedef enum pn_ia32_XorMem {
3484  pn_ia32_XorMem_unused = 0,
3485  pn_ia32_XorMem_flags = 1,
3486  pn_ia32_XorMem_M = 2,
3487 } pn_ia32_XorMem;
3488 
3489 typedef enum n_ia32_XorMem {
3490  n_ia32_XorMem_base = 0,
3491  n_ia32_XorMem_index = 1,
3492  n_ia32_XorMem_mem = 2,
3493  n_ia32_XorMem_val = 3,
3494 } n_ia32_XorMem;
3495 
3496 typedef enum pn_ia32_Xorp {
3497  pn_ia32_Xorp_res = 0,
3498  pn_ia32_Xorp_flags = 1,
3499  pn_ia32_Xorp_M = 2,
3500 } pn_ia32_Xorp;
3501 
3502 typedef enum n_ia32_Xorp {
3503  n_ia32_Xorp_base = 0,
3504  n_ia32_Xorp_index = 1,
3505  n_ia32_Xorp_mem = 2,
3506  n_ia32_Xorp_left = 3,
3507  n_ia32_Xorp_right = 4,
3508 } n_ia32_Xorp;
3509 
3510 typedef enum n_ia32_fabs {
3511  n_ia32_fabs_value = 0,
3512 } n_ia32_fabs;
3513 
3514 typedef enum pn_ia32_fadd {
3515  pn_ia32_fadd_res = 0,
3516  pn_ia32_fadd_dummy = 1,
3517  pn_ia32_fadd_M = 2,
3518 } pn_ia32_fadd;
3519 
3520 typedef enum n_ia32_fadd {
3521  n_ia32_fadd_base = 0,
3522  n_ia32_fadd_index = 1,
3523  n_ia32_fadd_mem = 2,
3524  n_ia32_fadd_left = 3,
3525  n_ia32_fadd_right = 4,
3526  n_ia32_fadd_fpcw = 5,
3527 } n_ia32_fadd;
3528 
3529 typedef enum n_ia32_fchs {
3530  n_ia32_fchs_value = 0,
3531 } n_ia32_fchs;
3532 
3533 typedef enum pn_ia32_fdiv {
3534  pn_ia32_fdiv_res = 0,
3535  pn_ia32_fdiv_dummy = 1,
3536  pn_ia32_fdiv_M = 2,
3537 } pn_ia32_fdiv;
3538 
3539 typedef enum n_ia32_fdiv {
3540  n_ia32_fdiv_base = 0,
3541  n_ia32_fdiv_index = 1,
3542  n_ia32_fdiv_mem = 2,
3543  n_ia32_fdiv_left = 3,
3544  n_ia32_fdiv_right = 4,
3545  n_ia32_fdiv_fpcw = 5,
3546 } n_ia32_fdiv;
3547 
3548 typedef enum n_ia32_fdup {
3549  n_ia32_fdup_val = 0,
3550 } n_ia32_fdup;
3551 
3552 typedef enum pn_ia32_fild {
3553  pn_ia32_fild_res = 0,
3554  pn_ia32_fild_unused = 1,
3555  pn_ia32_fild_M = 2,
3556 } pn_ia32_fild;
3557 
3558 typedef enum n_ia32_fild {
3559  n_ia32_fild_base = 0,
3560  n_ia32_fild_index = 1,
3561  n_ia32_fild_mem = 2,
3562 } n_ia32_fild;
3563 
3564 typedef enum pn_ia32_fist {
3565  pn_ia32_fist_M = 0,
3566  pn_ia32_fist_X_regular = 1,
3567  pn_ia32_fist_X_except = 2,
3568 } pn_ia32_fist;
3569 
3570 typedef enum n_ia32_fist {
3571  n_ia32_fist_base = 0,
3572  n_ia32_fist_index = 1,
3573  n_ia32_fist_mem = 2,
3574  n_ia32_fist_val = 3,
3575  n_ia32_fist_fpcw = 4,
3576 } n_ia32_fist;
3577 
3578 typedef enum pn_ia32_fistp {
3579  pn_ia32_fistp_M = 0,
3580  pn_ia32_fistp_X_regular = 1,
3581  pn_ia32_fistp_X_except = 2,
3582 } pn_ia32_fistp;
3583 
3584 typedef enum n_ia32_fistp {
3585  n_ia32_fistp_base = 0,
3586  n_ia32_fistp_index = 1,
3587  n_ia32_fistp_mem = 2,
3588  n_ia32_fistp_val = 3,
3589  n_ia32_fistp_fpcw = 4,
3590 } n_ia32_fistp;
3591 
3592 typedef enum pn_ia32_fisttp {
3593  pn_ia32_fisttp_M = 0,
3594  pn_ia32_fisttp_X_regular = 1,
3595  pn_ia32_fisttp_X_except = 2,
3596 } pn_ia32_fisttp;
3597 
3598 typedef enum n_ia32_fisttp {
3599  n_ia32_fisttp_base = 0,
3600  n_ia32_fisttp_index = 1,
3601  n_ia32_fisttp_mem = 2,
3602  n_ia32_fisttp_val = 3,
3603 } n_ia32_fisttp;
3604 
3605 typedef enum pn_ia32_fld {
3606  pn_ia32_fld_res = 0,
3607  pn_ia32_fld_unused = 1,
3608  pn_ia32_fld_M = 2,
3609  pn_ia32_fld_X_regular = 3,
3610  pn_ia32_fld_X_except = 4,
3611 } pn_ia32_fld;
3612 
3613 typedef enum n_ia32_fld {
3614  n_ia32_fld_base = 0,
3615  n_ia32_fld_index = 1,
3616  n_ia32_fld_mem = 2,
3617 } n_ia32_fld;
3618 
3619 typedef enum pn_ia32_fld1 {
3620  pn_ia32_fld1_res = 0,
3621 } pn_ia32_fld1;
3622 
3623 typedef enum pn_ia32_fldl2e {
3624  pn_ia32_fldl2e_res = 0,
3625 } pn_ia32_fldl2e;
3626 
3627 typedef enum pn_ia32_fldl2t {
3628  pn_ia32_fldl2t_res = 0,
3629 } pn_ia32_fldl2t;
3630 
3631 typedef enum pn_ia32_fldlg2 {
3632  pn_ia32_fldlg2_res = 0,
3633 } pn_ia32_fldlg2;
3634 
3635 typedef enum pn_ia32_fldln2 {
3636  pn_ia32_fldln2_res = 0,
3637 } pn_ia32_fldln2;
3638 
3639 typedef enum pn_ia32_fldpi {
3640  pn_ia32_fldpi_res = 0,
3641 } pn_ia32_fldpi;
3642 
3643 typedef enum pn_ia32_fldz {
3644  pn_ia32_fldz_res = 0,
3645 } pn_ia32_fldz;
3646 
3647 typedef enum pn_ia32_fmul {
3648  pn_ia32_fmul_res = 0,
3649  pn_ia32_fmul_dummy = 1,
3650  pn_ia32_fmul_M = 2,
3651 } pn_ia32_fmul;
3652 
3653 typedef enum n_ia32_fmul {
3654  n_ia32_fmul_base = 0,
3655  n_ia32_fmul_index = 1,
3656  n_ia32_fmul_mem = 2,
3657  n_ia32_fmul_left = 3,
3658  n_ia32_fmul_right = 4,
3659  n_ia32_fmul_fpcw = 5,
3660 } n_ia32_fmul;
3661 
3662 typedef enum pn_ia32_fst {
3663  pn_ia32_fst_M = 0,
3664  pn_ia32_fst_X_regular = 1,
3665  pn_ia32_fst_X_except = 2,
3666 } pn_ia32_fst;
3667 
3668 typedef enum n_ia32_fst {
3669  n_ia32_fst_base = 0,
3670  n_ia32_fst_index = 1,
3671  n_ia32_fst_mem = 2,
3672  n_ia32_fst_val = 3,
3673 } n_ia32_fst;
3674 
3675 typedef enum pn_ia32_fstp {
3676  pn_ia32_fstp_M = 0,
3677  pn_ia32_fstp_X_regular = 1,
3678  pn_ia32_fstp_X_except = 2,
3679 } pn_ia32_fstp;
3680 
3681 typedef enum n_ia32_fstp {
3682  n_ia32_fstp_base = 0,
3683  n_ia32_fstp_index = 1,
3684  n_ia32_fstp_mem = 2,
3685  n_ia32_fstp_val = 3,
3686 } n_ia32_fstp;
3687 
3688 typedef enum pn_ia32_fsub {
3689  pn_ia32_fsub_res = 0,
3690  pn_ia32_fsub_dummy = 1,
3691  pn_ia32_fsub_M = 2,
3692 } pn_ia32_fsub;
3693 
3694 typedef enum n_ia32_fsub {
3695  n_ia32_fsub_base = 0,
3696  n_ia32_fsub_index = 1,
3697  n_ia32_fsub_mem = 2,
3698  n_ia32_fsub_left = 3,
3699  n_ia32_fsub_right = 4,
3700  n_ia32_fsub_fpcw = 5,
3701 } n_ia32_fsub;
3702 
3703 typedef enum n_ia32_l_Adc {
3704  n_ia32_l_Adc_left = 0,
3705  n_ia32_l_Adc_right = 1,
3706  n_ia32_l_Adc_eflags = 2,
3707 } n_ia32_l_Adc;
3708 
3709 typedef enum pn_ia32_l_Add {
3710  pn_ia32_l_Add_res = 0,
3711  pn_ia32_l_Add_flags = 1,
3712 } pn_ia32_l_Add;
3713 
3714 typedef enum n_ia32_l_Add {
3715  n_ia32_l_Add_left = 0,
3716  n_ia32_l_Add_right = 1,
3717 } n_ia32_l_Add;
3718 
3719 typedef enum pn_ia32_l_FloattoLL {
3720  pn_ia32_l_FloattoLL_res_high = 0,
3721  pn_ia32_l_FloattoLL_res_low = 1,
3722 } pn_ia32_l_FloattoLL;
3723 
3724 typedef enum n_ia32_l_FloattoLL {
3725  n_ia32_l_FloattoLL_val = 0,
3726 } n_ia32_l_FloattoLL;
3727 
3728 typedef enum pn_ia32_l_IMul {
3729  pn_ia32_l_IMul_res_low = 0,
3730  pn_ia32_l_IMul_flags = 1,
3731  pn_ia32_l_IMul_M = 2,
3732  pn_ia32_l_IMul_res_high = 3,
3733 } pn_ia32_l_IMul;
3734 
3735 typedef enum n_ia32_l_IMul {
3736  n_ia32_l_IMul_left = 0,
3737  n_ia32_l_IMul_right = 1,
3738 } n_ia32_l_IMul;
3739 
3740 typedef enum n_ia32_l_LLtoFloat {
3741  n_ia32_l_LLtoFloat_val_high = 0,
3742  n_ia32_l_LLtoFloat_val_low = 1,
3743 } n_ia32_l_LLtoFloat;
3744 
3745 typedef enum pn_ia32_l_Minus64 {
3746  pn_ia32_l_Minus64_res_low = 0,
3747  pn_ia32_l_Minus64_res_high = 1,
3748 } pn_ia32_l_Minus64;
3749 
3750 typedef enum n_ia32_l_Minus64 {
3751  n_ia32_l_Minus64_low = 0,
3752  n_ia32_l_Minus64_high = 1,
3753 } n_ia32_l_Minus64;
3754 
3755 typedef enum pn_ia32_l_Mul {
3756  pn_ia32_l_Mul_res_low = 0,
3757  pn_ia32_l_Mul_flags = 1,
3758  pn_ia32_l_Mul_M = 2,
3759  pn_ia32_l_Mul_res_high = 3,
3760 } pn_ia32_l_Mul;
3761 
3762 typedef enum n_ia32_l_Mul {
3763  n_ia32_l_Mul_left = 0,
3764  n_ia32_l_Mul_right = 1,
3765 } n_ia32_l_Mul;
3766 
3767 typedef enum n_ia32_l_Sbb {
3768  n_ia32_l_Sbb_minuend = 0,
3769  n_ia32_l_Sbb_subtrahend = 1,
3770  n_ia32_l_Sbb_eflags = 2,
3771 } n_ia32_l_Sbb;
3772 
3773 typedef enum pn_ia32_l_Sub {
3774  pn_ia32_l_Sub_res = 0,
3775  pn_ia32_l_Sub_flags = 1,
3776 } pn_ia32_l_Sub;
3777 
3778 typedef enum n_ia32_l_Sub {
3779  n_ia32_l_Sub_minuend = 0,
3780  n_ia32_l_Sub_subtrahend = 1,
3781 } n_ia32_l_Sub;
3782 
3783 typedef enum pn_ia32_xAllOnes {
3784  pn_ia32_xAllOnes_res = 0,
3785 } pn_ia32_xAllOnes;
3786 
3787 typedef enum pn_ia32_xLoad {
3788  pn_ia32_xLoad_res = 0,
3789  pn_ia32_xLoad_unused = 1,
3790  pn_ia32_xLoad_M = 2,
3791  pn_ia32_xLoad_X_regular = 3,
3792  pn_ia32_xLoad_X_except = 4,
3793 } pn_ia32_xLoad;
3794 
3795 typedef enum n_ia32_xLoad {
3796  n_ia32_xLoad_base = 0,
3797  n_ia32_xLoad_index = 1,
3798  n_ia32_xLoad_mem = 2,
3799 } n_ia32_xLoad;
3800 
3801 typedef enum pn_ia32_xPzero {
3802  pn_ia32_xPzero_res = 0,
3803 } pn_ia32_xPzero;
3804 
3805 typedef enum pn_ia32_xStore {
3806  pn_ia32_xStore_M = 0,
3807  pn_ia32_xStore_X_regular = 1,
3808  pn_ia32_xStore_X_except = 2,
3809 } pn_ia32_xStore;
3810 
3811 typedef enum n_ia32_xStore {
3812  n_ia32_xStore_base = 0,
3813  n_ia32_xStore_index = 1,
3814  n_ia32_xStore_mem = 2,
3815  n_ia32_xStore_val = 3,
3816 } n_ia32_xStore;
3817 
3818 typedef enum pn_ia32_xZero {
3819  pn_ia32_xZero_res = 0,
3820 } pn_ia32_xZero;
3821 
3822 typedef enum pn_ia32_xxLoad {
3823  pn_ia32_xxLoad_res = 0,
3824  pn_ia32_xxLoad_M = 1,
3825  pn_ia32_xxLoad_X_regular = 2,
3826  pn_ia32_xxLoad_X_except = 3,
3827 } pn_ia32_xxLoad;
3828 
3829 typedef enum n_ia32_xxLoad {
3830  n_ia32_xxLoad_base = 0,
3831  n_ia32_xxLoad_index = 1,
3832  n_ia32_xxLoad_mem = 2,
3833 } n_ia32_xxLoad;
3834 
3835 typedef enum pn_ia32_xxStore {
3836  pn_ia32_xxStore_M = 0,
3837  pn_ia32_xxStore_X_regular = 1,
3838  pn_ia32_xxStore_X_except = 2,
3839 } pn_ia32_xxStore;
3840 
3841 typedef enum n_ia32_xxStore {
3842  n_ia32_xxStore_base = 0,
3843  n_ia32_xxStore_index = 1,
3844  n_ia32_xxStore_mem = 2,
3845  n_ia32_xxStore_val = 3,
3846 } n_ia32_xxStore;
3847 
3848 
3849 #endif
ir_op
struct ir_op ir_op
Node Opcode.
Definition: firm_types.h:56
dbg_info
struct dbg_info dbg_info
Source Reference.
Definition: firm_types.h:40
get_irn_op
ir_op * get_irn_op(const ir_node *node)
Returns the opcode struct of the node.
ir_switch_table
struct ir_switch_table ir_switch_table
A switch table mapping integer numbers to proj-numbers of a Switch-node.
Definition: firm_types.h:102
ir_mode
struct ir_mode ir_mode
SSA Value mode.
Definition: firm_types.h:59
ir_entity
struct ir_entity ir_entity
Entity.
Definition: firm_types.h:83
ir_node
struct ir_node ir_node
Procedure Graph Node.
Definition: firm_types.h:53