libFirm
gen_sparc_regalloc_if.c
1 
11 #include "gen_sparc_regalloc_if.h"
12 
13 #include "sparc_bearch_t.h"
14 
15 const arch_register_req_t sparc_class_reg_req_flags = {
16  .cls = &sparc_reg_classes[CLASS_sparc_flags],
17  .width = 1,
18 };
19 static const unsigned sparc_limited_flags_psr[] = { (1U << REG_FLAGS_PSR) };
20 const arch_register_req_t sparc_single_reg_req_flags_psr = {
21  .cls = &sparc_reg_classes[CLASS_sparc_flags],
22  .limited = sparc_limited_flags_psr,
23  .width = 1,
24 };
25 const arch_register_req_t sparc_class_reg_req_fp = {
26  .cls = &sparc_reg_classes[CLASS_sparc_fp],
27  .width = 1,
28 };
29 static const unsigned sparc_limited_fp_f0[] = { (1U << REG_FP_F0), 0 };
30 const arch_register_req_t sparc_single_reg_req_fp_f0 = {
31  .cls = &sparc_reg_classes[CLASS_sparc_fp],
32  .limited = sparc_limited_fp_f0,
33  .width = 1,
34 };
35 static const unsigned sparc_limited_fp_f1[] = { (1U << REG_FP_F1), 0 };
36 const arch_register_req_t sparc_single_reg_req_fp_f1 = {
37  .cls = &sparc_reg_classes[CLASS_sparc_fp],
38  .limited = sparc_limited_fp_f1,
39  .width = 1,
40 };
41 static const unsigned sparc_limited_fp_f2[] = { (1U << REG_FP_F2), 0 };
42 const arch_register_req_t sparc_single_reg_req_fp_f2 = {
43  .cls = &sparc_reg_classes[CLASS_sparc_fp],
44  .limited = sparc_limited_fp_f2,
45  .width = 1,
46 };
47 static const unsigned sparc_limited_fp_f3[] = { (1U << REG_FP_F3), 0 };
48 const arch_register_req_t sparc_single_reg_req_fp_f3 = {
49  .cls = &sparc_reg_classes[CLASS_sparc_fp],
50  .limited = sparc_limited_fp_f3,
51  .width = 1,
52 };
53 static const unsigned sparc_limited_fp_f4[] = { (1U << REG_FP_F4), 0 };
54 const arch_register_req_t sparc_single_reg_req_fp_f4 = {
55  .cls = &sparc_reg_classes[CLASS_sparc_fp],
56  .limited = sparc_limited_fp_f4,
57  .width = 1,
58 };
59 static const unsigned sparc_limited_fp_f5[] = { (1U << REG_FP_F5), 0 };
60 const arch_register_req_t sparc_single_reg_req_fp_f5 = {
61  .cls = &sparc_reg_classes[CLASS_sparc_fp],
62  .limited = sparc_limited_fp_f5,
63  .width = 1,
64 };
65 static const unsigned sparc_limited_fp_f6[] = { (1U << REG_FP_F6), 0 };
66 const arch_register_req_t sparc_single_reg_req_fp_f6 = {
67  .cls = &sparc_reg_classes[CLASS_sparc_fp],
68  .limited = sparc_limited_fp_f6,
69  .width = 1,
70 };
71 static const unsigned sparc_limited_fp_f7[] = { (1U << REG_FP_F7), 0 };
72 const arch_register_req_t sparc_single_reg_req_fp_f7 = {
73  .cls = &sparc_reg_classes[CLASS_sparc_fp],
74  .limited = sparc_limited_fp_f7,
75  .width = 1,
76 };
77 static const unsigned sparc_limited_fp_f8[] = { (1U << REG_FP_F8), 0 };
78 const arch_register_req_t sparc_single_reg_req_fp_f8 = {
79  .cls = &sparc_reg_classes[CLASS_sparc_fp],
80  .limited = sparc_limited_fp_f8,
81  .width = 1,
82 };
83 static const unsigned sparc_limited_fp_f9[] = { (1U << REG_FP_F9), 0 };
84 const arch_register_req_t sparc_single_reg_req_fp_f9 = {
85  .cls = &sparc_reg_classes[CLASS_sparc_fp],
86  .limited = sparc_limited_fp_f9,
87  .width = 1,
88 };
89 static const unsigned sparc_limited_fp_f10[] = { (1U << REG_FP_F10), 0 };
90 const arch_register_req_t sparc_single_reg_req_fp_f10 = {
91  .cls = &sparc_reg_classes[CLASS_sparc_fp],
92  .limited = sparc_limited_fp_f10,
93  .width = 1,
94 };
95 static const unsigned sparc_limited_fp_f11[] = { (1U << REG_FP_F11), 0 };
96 const arch_register_req_t sparc_single_reg_req_fp_f11 = {
97  .cls = &sparc_reg_classes[CLASS_sparc_fp],
98  .limited = sparc_limited_fp_f11,
99  .width = 1,
100 };
101 static const unsigned sparc_limited_fp_f12[] = { (1U << REG_FP_F12), 0 };
102 const arch_register_req_t sparc_single_reg_req_fp_f12 = {
103  .cls = &sparc_reg_classes[CLASS_sparc_fp],
104  .limited = sparc_limited_fp_f12,
105  .width = 1,
106 };
107 static const unsigned sparc_limited_fp_f13[] = { (1U << REG_FP_F13), 0 };
108 const arch_register_req_t sparc_single_reg_req_fp_f13 = {
109  .cls = &sparc_reg_classes[CLASS_sparc_fp],
110  .limited = sparc_limited_fp_f13,
111  .width = 1,
112 };
113 static const unsigned sparc_limited_fp_f14[] = { (1U << REG_FP_F14), 0 };
114 const arch_register_req_t sparc_single_reg_req_fp_f14 = {
115  .cls = &sparc_reg_classes[CLASS_sparc_fp],
116  .limited = sparc_limited_fp_f14,
117  .width = 1,
118 };
119 static const unsigned sparc_limited_fp_f15[] = { (1U << REG_FP_F15), 0 };
120 const arch_register_req_t sparc_single_reg_req_fp_f15 = {
121  .cls = &sparc_reg_classes[CLASS_sparc_fp],
122  .limited = sparc_limited_fp_f15,
123  .width = 1,
124 };
125 static const unsigned sparc_limited_fp_f16[] = { (1U << REG_FP_F16), 0 };
126 const arch_register_req_t sparc_single_reg_req_fp_f16 = {
127  .cls = &sparc_reg_classes[CLASS_sparc_fp],
128  .limited = sparc_limited_fp_f16,
129  .width = 1,
130 };
131 static const unsigned sparc_limited_fp_f17[] = { (1U << REG_FP_F17), 0 };
132 const arch_register_req_t sparc_single_reg_req_fp_f17 = {
133  .cls = &sparc_reg_classes[CLASS_sparc_fp],
134  .limited = sparc_limited_fp_f17,
135  .width = 1,
136 };
137 static const unsigned sparc_limited_fp_f18[] = { (1U << REG_FP_F18), 0 };
138 const arch_register_req_t sparc_single_reg_req_fp_f18 = {
139  .cls = &sparc_reg_classes[CLASS_sparc_fp],
140  .limited = sparc_limited_fp_f18,
141  .width = 1,
142 };
143 static const unsigned sparc_limited_fp_f19[] = { (1U << REG_FP_F19), 0 };
144 const arch_register_req_t sparc_single_reg_req_fp_f19 = {
145  .cls = &sparc_reg_classes[CLASS_sparc_fp],
146  .limited = sparc_limited_fp_f19,
147  .width = 1,
148 };
149 static const unsigned sparc_limited_fp_f20[] = { (1U << REG_FP_F20), 0 };
150 const arch_register_req_t sparc_single_reg_req_fp_f20 = {
151  .cls = &sparc_reg_classes[CLASS_sparc_fp],
152  .limited = sparc_limited_fp_f20,
153  .width = 1,
154 };
155 static const unsigned sparc_limited_fp_f21[] = { (1U << REG_FP_F21), 0 };
156 const arch_register_req_t sparc_single_reg_req_fp_f21 = {
157  .cls = &sparc_reg_classes[CLASS_sparc_fp],
158  .limited = sparc_limited_fp_f21,
159  .width = 1,
160 };
161 static const unsigned sparc_limited_fp_f22[] = { (1U << REG_FP_F22), 0 };
162 const arch_register_req_t sparc_single_reg_req_fp_f22 = {
163  .cls = &sparc_reg_classes[CLASS_sparc_fp],
164  .limited = sparc_limited_fp_f22,
165  .width = 1,
166 };
167 static const unsigned sparc_limited_fp_f23[] = { (1U << REG_FP_F23), 0 };
168 const arch_register_req_t sparc_single_reg_req_fp_f23 = {
169  .cls = &sparc_reg_classes[CLASS_sparc_fp],
170  .limited = sparc_limited_fp_f23,
171  .width = 1,
172 };
173 static const unsigned sparc_limited_fp_f24[] = { (1U << REG_FP_F24), 0 };
174 const arch_register_req_t sparc_single_reg_req_fp_f24 = {
175  .cls = &sparc_reg_classes[CLASS_sparc_fp],
176  .limited = sparc_limited_fp_f24,
177  .width = 1,
178 };
179 static const unsigned sparc_limited_fp_f25[] = { (1U << REG_FP_F25), 0 };
180 const arch_register_req_t sparc_single_reg_req_fp_f25 = {
181  .cls = &sparc_reg_classes[CLASS_sparc_fp],
182  .limited = sparc_limited_fp_f25,
183  .width = 1,
184 };
185 static const unsigned sparc_limited_fp_f26[] = { (1U << REG_FP_F26), 0 };
186 const arch_register_req_t sparc_single_reg_req_fp_f26 = {
187  .cls = &sparc_reg_classes[CLASS_sparc_fp],
188  .limited = sparc_limited_fp_f26,
189  .width = 1,
190 };
191 static const unsigned sparc_limited_fp_f27[] = { (1U << REG_FP_F27), 0 };
192 const arch_register_req_t sparc_single_reg_req_fp_f27 = {
193  .cls = &sparc_reg_classes[CLASS_sparc_fp],
194  .limited = sparc_limited_fp_f27,
195  .width = 1,
196 };
197 static const unsigned sparc_limited_fp_f28[] = { (1U << REG_FP_F28), 0 };
198 const arch_register_req_t sparc_single_reg_req_fp_f28 = {
199  .cls = &sparc_reg_classes[CLASS_sparc_fp],
200  .limited = sparc_limited_fp_f28,
201  .width = 1,
202 };
203 static const unsigned sparc_limited_fp_f29[] = { (1U << REG_FP_F29), 0 };
204 const arch_register_req_t sparc_single_reg_req_fp_f29 = {
205  .cls = &sparc_reg_classes[CLASS_sparc_fp],
206  .limited = sparc_limited_fp_f29,
207  .width = 1,
208 };
209 static const unsigned sparc_limited_fp_f30[] = { (1U << REG_FP_F30), 0 };
210 const arch_register_req_t sparc_single_reg_req_fp_f30 = {
211  .cls = &sparc_reg_classes[CLASS_sparc_fp],
212  .limited = sparc_limited_fp_f30,
213  .width = 1,
214 };
215 static const unsigned sparc_limited_fp_f31[] = { (1U << REG_FP_F31), 0 };
216 const arch_register_req_t sparc_single_reg_req_fp_f31 = {
217  .cls = &sparc_reg_classes[CLASS_sparc_fp],
218  .limited = sparc_limited_fp_f31,
219  .width = 1,
220 };
221 const arch_register_req_t sparc_class_reg_req_fpflags = {
222  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
223  .width = 1,
224 };
225 static const unsigned sparc_limited_fpflags_fsr[] = { (1U << REG_FPFLAGS_FSR) };
226 const arch_register_req_t sparc_single_reg_req_fpflags_fsr = {
227  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
228  .limited = sparc_limited_fpflags_fsr,
229  .width = 1,
230 };
231 const arch_register_req_t sparc_class_reg_req_gp = {
232  .cls = &sparc_reg_classes[CLASS_sparc_gp],
233  .width = 1,
234 };
235 static const unsigned sparc_limited_gp_l0[] = { (1U << REG_GP_L0), 0 };
236 const arch_register_req_t sparc_single_reg_req_gp_l0 = {
237  .cls = &sparc_reg_classes[CLASS_sparc_gp],
238  .limited = sparc_limited_gp_l0,
239  .width = 1,
240 };
241 static const unsigned sparc_limited_gp_l1[] = { (1U << REG_GP_L1), 0 };
242 const arch_register_req_t sparc_single_reg_req_gp_l1 = {
243  .cls = &sparc_reg_classes[CLASS_sparc_gp],
244  .limited = sparc_limited_gp_l1,
245  .width = 1,
246 };
247 static const unsigned sparc_limited_gp_l2[] = { (1U << REG_GP_L2), 0 };
248 const arch_register_req_t sparc_single_reg_req_gp_l2 = {
249  .cls = &sparc_reg_classes[CLASS_sparc_gp],
250  .limited = sparc_limited_gp_l2,
251  .width = 1,
252 };
253 static const unsigned sparc_limited_gp_l3[] = { (1U << REG_GP_L3), 0 };
254 const arch_register_req_t sparc_single_reg_req_gp_l3 = {
255  .cls = &sparc_reg_classes[CLASS_sparc_gp],
256  .limited = sparc_limited_gp_l3,
257  .width = 1,
258 };
259 static const unsigned sparc_limited_gp_l4[] = { (1U << REG_GP_L4), 0 };
260 const arch_register_req_t sparc_single_reg_req_gp_l4 = {
261  .cls = &sparc_reg_classes[CLASS_sparc_gp],
262  .limited = sparc_limited_gp_l4,
263  .width = 1,
264 };
265 static const unsigned sparc_limited_gp_l5[] = { (1U << REG_GP_L5), 0 };
266 const arch_register_req_t sparc_single_reg_req_gp_l5 = {
267  .cls = &sparc_reg_classes[CLASS_sparc_gp],
268  .limited = sparc_limited_gp_l5,
269  .width = 1,
270 };
271 static const unsigned sparc_limited_gp_l6[] = { (1U << REG_GP_L6), 0 };
272 const arch_register_req_t sparc_single_reg_req_gp_l6 = {
273  .cls = &sparc_reg_classes[CLASS_sparc_gp],
274  .limited = sparc_limited_gp_l6,
275  .width = 1,
276 };
277 static const unsigned sparc_limited_gp_l7[] = { (1U << REG_GP_L7), 0 };
278 const arch_register_req_t sparc_single_reg_req_gp_l7 = {
279  .cls = &sparc_reg_classes[CLASS_sparc_gp],
280  .limited = sparc_limited_gp_l7,
281  .width = 1,
282 };
283 static const unsigned sparc_limited_gp_g0[] = { (1U << REG_GP_G0), 0 };
284 const arch_register_req_t sparc_single_reg_req_gp_g0 = {
285  .cls = &sparc_reg_classes[CLASS_sparc_gp],
286  .limited = sparc_limited_gp_g0,
287  .width = 1,
288 };
289 static const unsigned sparc_limited_gp_g1[] = { (1U << REG_GP_G1), 0 };
290 const arch_register_req_t sparc_single_reg_req_gp_g1 = {
291  .cls = &sparc_reg_classes[CLASS_sparc_gp],
292  .limited = sparc_limited_gp_g1,
293  .width = 1,
294 };
295 static const unsigned sparc_limited_gp_g2[] = { (1U << REG_GP_G2), 0 };
296 const arch_register_req_t sparc_single_reg_req_gp_g2 = {
297  .cls = &sparc_reg_classes[CLASS_sparc_gp],
298  .limited = sparc_limited_gp_g2,
299  .width = 1,
300 };
301 static const unsigned sparc_limited_gp_g3[] = { (1U << REG_GP_G3), 0 };
302 const arch_register_req_t sparc_single_reg_req_gp_g3 = {
303  .cls = &sparc_reg_classes[CLASS_sparc_gp],
304  .limited = sparc_limited_gp_g3,
305  .width = 1,
306 };
307 static const unsigned sparc_limited_gp_g4[] = { (1U << REG_GP_G4), 0 };
308 const arch_register_req_t sparc_single_reg_req_gp_g4 = {
309  .cls = &sparc_reg_classes[CLASS_sparc_gp],
310  .limited = sparc_limited_gp_g4,
311  .width = 1,
312 };
313 static const unsigned sparc_limited_gp_g5[] = { (1U << REG_GP_G5), 0 };
314 const arch_register_req_t sparc_single_reg_req_gp_g5 = {
315  .cls = &sparc_reg_classes[CLASS_sparc_gp],
316  .limited = sparc_limited_gp_g5,
317  .width = 1,
318 };
319 static const unsigned sparc_limited_gp_g6[] = { (1U << REG_GP_G6), 0 };
320 const arch_register_req_t sparc_single_reg_req_gp_g6 = {
321  .cls = &sparc_reg_classes[CLASS_sparc_gp],
322  .limited = sparc_limited_gp_g6,
323  .width = 1,
324 };
325 static const unsigned sparc_limited_gp_g7[] = { (1U << REG_GP_G7), 0 };
326 const arch_register_req_t sparc_single_reg_req_gp_g7 = {
327  .cls = &sparc_reg_classes[CLASS_sparc_gp],
328  .limited = sparc_limited_gp_g7,
329  .width = 1,
330 };
331 static const unsigned sparc_limited_gp_o0[] = { (1U << REG_GP_O0), 0 };
332 const arch_register_req_t sparc_single_reg_req_gp_o0 = {
333  .cls = &sparc_reg_classes[CLASS_sparc_gp],
334  .limited = sparc_limited_gp_o0,
335  .width = 1,
336 };
337 static const unsigned sparc_limited_gp_o1[] = { (1U << REG_GP_O1), 0 };
338 const arch_register_req_t sparc_single_reg_req_gp_o1 = {
339  .cls = &sparc_reg_classes[CLASS_sparc_gp],
340  .limited = sparc_limited_gp_o1,
341  .width = 1,
342 };
343 static const unsigned sparc_limited_gp_o2[] = { (1U << REG_GP_O2), 0 };
344 const arch_register_req_t sparc_single_reg_req_gp_o2 = {
345  .cls = &sparc_reg_classes[CLASS_sparc_gp],
346  .limited = sparc_limited_gp_o2,
347  .width = 1,
348 };
349 static const unsigned sparc_limited_gp_o3[] = { (1U << REG_GP_O3), 0 };
350 const arch_register_req_t sparc_single_reg_req_gp_o3 = {
351  .cls = &sparc_reg_classes[CLASS_sparc_gp],
352  .limited = sparc_limited_gp_o3,
353  .width = 1,
354 };
355 static const unsigned sparc_limited_gp_o4[] = { (1U << REG_GP_O4), 0 };
356 const arch_register_req_t sparc_single_reg_req_gp_o4 = {
357  .cls = &sparc_reg_classes[CLASS_sparc_gp],
358  .limited = sparc_limited_gp_o4,
359  .width = 1,
360 };
361 static const unsigned sparc_limited_gp_o5[] = { (1U << REG_GP_O5), 0 };
362 const arch_register_req_t sparc_single_reg_req_gp_o5 = {
363  .cls = &sparc_reg_classes[CLASS_sparc_gp],
364  .limited = sparc_limited_gp_o5,
365  .width = 1,
366 };
367 static const unsigned sparc_limited_gp_sp[] = { (1U << REG_GP_SP), 0 };
368 const arch_register_req_t sparc_single_reg_req_gp_sp = {
369  .cls = &sparc_reg_classes[CLASS_sparc_gp],
370  .limited = sparc_limited_gp_sp,
371  .width = 1,
372 };
373 static const unsigned sparc_limited_gp_o7[] = { (1U << REG_GP_O7), 0 };
374 const arch_register_req_t sparc_single_reg_req_gp_o7 = {
375  .cls = &sparc_reg_classes[CLASS_sparc_gp],
376  .limited = sparc_limited_gp_o7,
377  .width = 1,
378 };
379 static const unsigned sparc_limited_gp_i0[] = { (1U << REG_GP_I0), 0 };
380 const arch_register_req_t sparc_single_reg_req_gp_i0 = {
381  .cls = &sparc_reg_classes[CLASS_sparc_gp],
382  .limited = sparc_limited_gp_i0,
383  .width = 1,
384 };
385 static const unsigned sparc_limited_gp_i1[] = { (1U << REG_GP_I1), 0 };
386 const arch_register_req_t sparc_single_reg_req_gp_i1 = {
387  .cls = &sparc_reg_classes[CLASS_sparc_gp],
388  .limited = sparc_limited_gp_i1,
389  .width = 1,
390 };
391 static const unsigned sparc_limited_gp_i2[] = { (1U << REG_GP_I2), 0 };
392 const arch_register_req_t sparc_single_reg_req_gp_i2 = {
393  .cls = &sparc_reg_classes[CLASS_sparc_gp],
394  .limited = sparc_limited_gp_i2,
395  .width = 1,
396 };
397 static const unsigned sparc_limited_gp_i3[] = { (1U << REG_GP_I3), 0 };
398 const arch_register_req_t sparc_single_reg_req_gp_i3 = {
399  .cls = &sparc_reg_classes[CLASS_sparc_gp],
400  .limited = sparc_limited_gp_i3,
401  .width = 1,
402 };
403 static const unsigned sparc_limited_gp_i4[] = { (1U << REG_GP_I4), 0 };
404 const arch_register_req_t sparc_single_reg_req_gp_i4 = {
405  .cls = &sparc_reg_classes[CLASS_sparc_gp],
406  .limited = sparc_limited_gp_i4,
407  .width = 1,
408 };
409 static const unsigned sparc_limited_gp_i5[] = { (1U << REG_GP_I5), 0 };
410 const arch_register_req_t sparc_single_reg_req_gp_i5 = {
411  .cls = &sparc_reg_classes[CLASS_sparc_gp],
412  .limited = sparc_limited_gp_i5,
413  .width = 1,
414 };
415 static const unsigned sparc_limited_gp_fp[] = { (1U << REG_GP_FP), 0 };
416 const arch_register_req_t sparc_single_reg_req_gp_fp = {
417  .cls = &sparc_reg_classes[CLASS_sparc_gp],
418  .limited = sparc_limited_gp_fp,
419  .width = 1,
420 };
421 static const unsigned sparc_limited_gp_i7[] = { (1U << REG_GP_I7), 0 };
422 const arch_register_req_t sparc_single_reg_req_gp_i7 = {
423  .cls = &sparc_reg_classes[CLASS_sparc_gp],
424  .limited = sparc_limited_gp_i7,
425  .width = 1,
426 };
427 const arch_register_req_t sparc_class_reg_req_mul_div_high_res = {
428  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
429  .width = 1,
430 };
431 static const unsigned sparc_limited_mul_div_high_res_y[] = { (1U << REG_MUL_DIV_HIGH_RES_Y) };
432 const arch_register_req_t sparc_single_reg_req_mul_div_high_res_y = {
433  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
434  .limited = sparc_limited_mul_div_high_res_y,
435  .width = 1,
436 };
437 
438 
439 arch_register_class_t sparc_reg_classes[] = {
440  {
441  .name = "sparc_flags",
442  .mode = NULL,
443  .regs = &sparc_registers[REG_PSR],
444  .class_req = &sparc_class_reg_req_flags,
445  .index = CLASS_sparc_flags,
446  .n_regs = 1,
447  .manual_ra = true,
448  },
449  {
450  .name = "sparc_fp",
451  .mode = NULL,
452  .regs = &sparc_registers[REG_F0],
453  .class_req = &sparc_class_reg_req_fp,
454  .index = CLASS_sparc_fp,
455  .n_regs = 32,
456  .manual_ra = false,
457  },
458  {
459  .name = "sparc_fpflags",
460  .mode = NULL,
461  .regs = &sparc_registers[REG_FSR],
462  .class_req = &sparc_class_reg_req_fpflags,
463  .index = CLASS_sparc_fpflags,
464  .n_regs = 1,
465  .manual_ra = true,
466  },
467  {
468  .name = "sparc_gp",
469  .mode = NULL,
470  .regs = &sparc_registers[REG_L0],
471  .class_req = &sparc_class_reg_req_gp,
472  .index = CLASS_sparc_gp,
473  .n_regs = 32,
474  .manual_ra = false,
475  },
476  {
477  .name = "sparc_mul_div_high_res",
478  .mode = NULL,
479  .regs = &sparc_registers[REG_Y],
480  .class_req = &sparc_class_reg_req_mul_div_high_res,
481  .index = CLASS_sparc_mul_div_high_res,
482  .n_regs = 1,
483  .manual_ra = true,
484  },
485 
486 };
487 
489 const arch_register_t sparc_registers[] = {
490  {
491  .name = "psr",
492  .cls = &sparc_reg_classes[CLASS_sparc_flags],
493  .single_req = &sparc_single_reg_req_flags_psr,
494  .index = REG_FLAGS_PSR,
495  .global_index = REG_PSR,
496  .dwarf_number = 0,
497  .encoding = REG_FLAGS_PSR,
498  .is_virtual = false,
499  },
500  {
501  .name = "f0",
502  .cls = &sparc_reg_classes[CLASS_sparc_fp],
503  .single_req = &sparc_single_reg_req_fp_f0,
504  .index = REG_FP_F0,
505  .global_index = REG_F0,
506  .dwarf_number = 32,
507  .encoding = 0,
508  .is_virtual = false,
509  },
510  {
511  .name = "f1",
512  .cls = &sparc_reg_classes[CLASS_sparc_fp],
513  .single_req = &sparc_single_reg_req_fp_f1,
514  .index = REG_FP_F1,
515  .global_index = REG_F1,
516  .dwarf_number = 33,
517  .encoding = 1,
518  .is_virtual = false,
519  },
520  {
521  .name = "f2",
522  .cls = &sparc_reg_classes[CLASS_sparc_fp],
523  .single_req = &sparc_single_reg_req_fp_f2,
524  .index = REG_FP_F2,
525  .global_index = REG_F2,
526  .dwarf_number = 34,
527  .encoding = 2,
528  .is_virtual = false,
529  },
530  {
531  .name = "f3",
532  .cls = &sparc_reg_classes[CLASS_sparc_fp],
533  .single_req = &sparc_single_reg_req_fp_f3,
534  .index = REG_FP_F3,
535  .global_index = REG_F3,
536  .dwarf_number = 35,
537  .encoding = 3,
538  .is_virtual = false,
539  },
540  {
541  .name = "f4",
542  .cls = &sparc_reg_classes[CLASS_sparc_fp],
543  .single_req = &sparc_single_reg_req_fp_f4,
544  .index = REG_FP_F4,
545  .global_index = REG_F4,
546  .dwarf_number = 36,
547  .encoding = 4,
548  .is_virtual = false,
549  },
550  {
551  .name = "f5",
552  .cls = &sparc_reg_classes[CLASS_sparc_fp],
553  .single_req = &sparc_single_reg_req_fp_f5,
554  .index = REG_FP_F5,
555  .global_index = REG_F5,
556  .dwarf_number = 37,
557  .encoding = 5,
558  .is_virtual = false,
559  },
560  {
561  .name = "f6",
562  .cls = &sparc_reg_classes[CLASS_sparc_fp],
563  .single_req = &sparc_single_reg_req_fp_f6,
564  .index = REG_FP_F6,
565  .global_index = REG_F6,
566  .dwarf_number = 38,
567  .encoding = 6,
568  .is_virtual = false,
569  },
570  {
571  .name = "f7",
572  .cls = &sparc_reg_classes[CLASS_sparc_fp],
573  .single_req = &sparc_single_reg_req_fp_f7,
574  .index = REG_FP_F7,
575  .global_index = REG_F7,
576  .dwarf_number = 39,
577  .encoding = 7,
578  .is_virtual = false,
579  },
580  {
581  .name = "f8",
582  .cls = &sparc_reg_classes[CLASS_sparc_fp],
583  .single_req = &sparc_single_reg_req_fp_f8,
584  .index = REG_FP_F8,
585  .global_index = REG_F8,
586  .dwarf_number = 40,
587  .encoding = 8,
588  .is_virtual = false,
589  },
590  {
591  .name = "f9",
592  .cls = &sparc_reg_classes[CLASS_sparc_fp],
593  .single_req = &sparc_single_reg_req_fp_f9,
594  .index = REG_FP_F9,
595  .global_index = REG_F9,
596  .dwarf_number = 41,
597  .encoding = 9,
598  .is_virtual = false,
599  },
600  {
601  .name = "f10",
602  .cls = &sparc_reg_classes[CLASS_sparc_fp],
603  .single_req = &sparc_single_reg_req_fp_f10,
604  .index = REG_FP_F10,
605  .global_index = REG_F10,
606  .dwarf_number = 42,
607  .encoding = 10,
608  .is_virtual = false,
609  },
610  {
611  .name = "f11",
612  .cls = &sparc_reg_classes[CLASS_sparc_fp],
613  .single_req = &sparc_single_reg_req_fp_f11,
614  .index = REG_FP_F11,
615  .global_index = REG_F11,
616  .dwarf_number = 43,
617  .encoding = 11,
618  .is_virtual = false,
619  },
620  {
621  .name = "f12",
622  .cls = &sparc_reg_classes[CLASS_sparc_fp],
623  .single_req = &sparc_single_reg_req_fp_f12,
624  .index = REG_FP_F12,
625  .global_index = REG_F12,
626  .dwarf_number = 44,
627  .encoding = 12,
628  .is_virtual = false,
629  },
630  {
631  .name = "f13",
632  .cls = &sparc_reg_classes[CLASS_sparc_fp],
633  .single_req = &sparc_single_reg_req_fp_f13,
634  .index = REG_FP_F13,
635  .global_index = REG_F13,
636  .dwarf_number = 45,
637  .encoding = 13,
638  .is_virtual = false,
639  },
640  {
641  .name = "f14",
642  .cls = &sparc_reg_classes[CLASS_sparc_fp],
643  .single_req = &sparc_single_reg_req_fp_f14,
644  .index = REG_FP_F14,
645  .global_index = REG_F14,
646  .dwarf_number = 46,
647  .encoding = 14,
648  .is_virtual = false,
649  },
650  {
651  .name = "f15",
652  .cls = &sparc_reg_classes[CLASS_sparc_fp],
653  .single_req = &sparc_single_reg_req_fp_f15,
654  .index = REG_FP_F15,
655  .global_index = REG_F15,
656  .dwarf_number = 47,
657  .encoding = 15,
658  .is_virtual = false,
659  },
660  {
661  .name = "f16",
662  .cls = &sparc_reg_classes[CLASS_sparc_fp],
663  .single_req = &sparc_single_reg_req_fp_f16,
664  .index = REG_FP_F16,
665  .global_index = REG_F16,
666  .dwarf_number = 48,
667  .encoding = 16,
668  .is_virtual = false,
669  },
670  {
671  .name = "f17",
672  .cls = &sparc_reg_classes[CLASS_sparc_fp],
673  .single_req = &sparc_single_reg_req_fp_f17,
674  .index = REG_FP_F17,
675  .global_index = REG_F17,
676  .dwarf_number = 49,
677  .encoding = 17,
678  .is_virtual = false,
679  },
680  {
681  .name = "f18",
682  .cls = &sparc_reg_classes[CLASS_sparc_fp],
683  .single_req = &sparc_single_reg_req_fp_f18,
684  .index = REG_FP_F18,
685  .global_index = REG_F18,
686  .dwarf_number = 50,
687  .encoding = 18,
688  .is_virtual = false,
689  },
690  {
691  .name = "f19",
692  .cls = &sparc_reg_classes[CLASS_sparc_fp],
693  .single_req = &sparc_single_reg_req_fp_f19,
694  .index = REG_FP_F19,
695  .global_index = REG_F19,
696  .dwarf_number = 51,
697  .encoding = 19,
698  .is_virtual = false,
699  },
700  {
701  .name = "f20",
702  .cls = &sparc_reg_classes[CLASS_sparc_fp],
703  .single_req = &sparc_single_reg_req_fp_f20,
704  .index = REG_FP_F20,
705  .global_index = REG_F20,
706  .dwarf_number = 52,
707  .encoding = 20,
708  .is_virtual = false,
709  },
710  {
711  .name = "f21",
712  .cls = &sparc_reg_classes[CLASS_sparc_fp],
713  .single_req = &sparc_single_reg_req_fp_f21,
714  .index = REG_FP_F21,
715  .global_index = REG_F21,
716  .dwarf_number = 53,
717  .encoding = 21,
718  .is_virtual = false,
719  },
720  {
721  .name = "f22",
722  .cls = &sparc_reg_classes[CLASS_sparc_fp],
723  .single_req = &sparc_single_reg_req_fp_f22,
724  .index = REG_FP_F22,
725  .global_index = REG_F22,
726  .dwarf_number = 54,
727  .encoding = 22,
728  .is_virtual = false,
729  },
730  {
731  .name = "f23",
732  .cls = &sparc_reg_classes[CLASS_sparc_fp],
733  .single_req = &sparc_single_reg_req_fp_f23,
734  .index = REG_FP_F23,
735  .global_index = REG_F23,
736  .dwarf_number = 55,
737  .encoding = 23,
738  .is_virtual = false,
739  },
740  {
741  .name = "f24",
742  .cls = &sparc_reg_classes[CLASS_sparc_fp],
743  .single_req = &sparc_single_reg_req_fp_f24,
744  .index = REG_FP_F24,
745  .global_index = REG_F24,
746  .dwarf_number = 56,
747  .encoding = 24,
748  .is_virtual = false,
749  },
750  {
751  .name = "f25",
752  .cls = &sparc_reg_classes[CLASS_sparc_fp],
753  .single_req = &sparc_single_reg_req_fp_f25,
754  .index = REG_FP_F25,
755  .global_index = REG_F25,
756  .dwarf_number = 57,
757  .encoding = 25,
758  .is_virtual = false,
759  },
760  {
761  .name = "f26",
762  .cls = &sparc_reg_classes[CLASS_sparc_fp],
763  .single_req = &sparc_single_reg_req_fp_f26,
764  .index = REG_FP_F26,
765  .global_index = REG_F26,
766  .dwarf_number = 58,
767  .encoding = 26,
768  .is_virtual = false,
769  },
770  {
771  .name = "f27",
772  .cls = &sparc_reg_classes[CLASS_sparc_fp],
773  .single_req = &sparc_single_reg_req_fp_f27,
774  .index = REG_FP_F27,
775  .global_index = REG_F27,
776  .dwarf_number = 59,
777  .encoding = 27,
778  .is_virtual = false,
779  },
780  {
781  .name = "f28",
782  .cls = &sparc_reg_classes[CLASS_sparc_fp],
783  .single_req = &sparc_single_reg_req_fp_f28,
784  .index = REG_FP_F28,
785  .global_index = REG_F28,
786  .dwarf_number = 60,
787  .encoding = 28,
788  .is_virtual = false,
789  },
790  {
791  .name = "f29",
792  .cls = &sparc_reg_classes[CLASS_sparc_fp],
793  .single_req = &sparc_single_reg_req_fp_f29,
794  .index = REG_FP_F29,
795  .global_index = REG_F29,
796  .dwarf_number = 61,
797  .encoding = 29,
798  .is_virtual = false,
799  },
800  {
801  .name = "f30",
802  .cls = &sparc_reg_classes[CLASS_sparc_fp],
803  .single_req = &sparc_single_reg_req_fp_f30,
804  .index = REG_FP_F30,
805  .global_index = REG_F30,
806  .dwarf_number = 62,
807  .encoding = 30,
808  .is_virtual = false,
809  },
810  {
811  .name = "f31",
812  .cls = &sparc_reg_classes[CLASS_sparc_fp],
813  .single_req = &sparc_single_reg_req_fp_f31,
814  .index = REG_FP_F31,
815  .global_index = REG_F31,
816  .dwarf_number = 63,
817  .encoding = 31,
818  .is_virtual = false,
819  },
820  {
821  .name = "fsr",
822  .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
823  .single_req = &sparc_single_reg_req_fpflags_fsr,
824  .index = REG_FPFLAGS_FSR,
825  .global_index = REG_FSR,
826  .dwarf_number = 0,
827  .encoding = REG_FPFLAGS_FSR,
828  .is_virtual = false,
829  },
830  {
831  .name = "l0",
832  .cls = &sparc_reg_classes[CLASS_sparc_gp],
833  .single_req = &sparc_single_reg_req_gp_l0,
834  .index = REG_GP_L0,
835  .global_index = REG_L0,
836  .dwarf_number = 16,
837  .encoding = 16,
838  .is_virtual = false,
839  },
840  {
841  .name = "l1",
842  .cls = &sparc_reg_classes[CLASS_sparc_gp],
843  .single_req = &sparc_single_reg_req_gp_l1,
844  .index = REG_GP_L1,
845  .global_index = REG_L1,
846  .dwarf_number = 17,
847  .encoding = 17,
848  .is_virtual = false,
849  },
850  {
851  .name = "l2",
852  .cls = &sparc_reg_classes[CLASS_sparc_gp],
853  .single_req = &sparc_single_reg_req_gp_l2,
854  .index = REG_GP_L2,
855  .global_index = REG_L2,
856  .dwarf_number = 18,
857  .encoding = 18,
858  .is_virtual = false,
859  },
860  {
861  .name = "l3",
862  .cls = &sparc_reg_classes[CLASS_sparc_gp],
863  .single_req = &sparc_single_reg_req_gp_l3,
864  .index = REG_GP_L3,
865  .global_index = REG_L3,
866  .dwarf_number = 19,
867  .encoding = 19,
868  .is_virtual = false,
869  },
870  {
871  .name = "l4",
872  .cls = &sparc_reg_classes[CLASS_sparc_gp],
873  .single_req = &sparc_single_reg_req_gp_l4,
874  .index = REG_GP_L4,
875  .global_index = REG_L4,
876  .dwarf_number = 20,
877  .encoding = 20,
878  .is_virtual = false,
879  },
880  {
881  .name = "l5",
882  .cls = &sparc_reg_classes[CLASS_sparc_gp],
883  .single_req = &sparc_single_reg_req_gp_l5,
884  .index = REG_GP_L5,
885  .global_index = REG_L5,
886  .dwarf_number = 21,
887  .encoding = 21,
888  .is_virtual = false,
889  },
890  {
891  .name = "l6",
892  .cls = &sparc_reg_classes[CLASS_sparc_gp],
893  .single_req = &sparc_single_reg_req_gp_l6,
894  .index = REG_GP_L6,
895  .global_index = REG_L6,
896  .dwarf_number = 22,
897  .encoding = 22,
898  .is_virtual = false,
899  },
900  {
901  .name = "l7",
902  .cls = &sparc_reg_classes[CLASS_sparc_gp],
903  .single_req = &sparc_single_reg_req_gp_l7,
904  .index = REG_GP_L7,
905  .global_index = REG_L7,
906  .dwarf_number = 23,
907  .encoding = 23,
908  .is_virtual = false,
909  },
910  {
911  .name = "g0",
912  .cls = &sparc_reg_classes[CLASS_sparc_gp],
913  .single_req = &sparc_single_reg_req_gp_g0,
914  .index = REG_GP_G0,
915  .global_index = REG_G0,
916  .dwarf_number = 0,
917  .encoding = 0,
918  .is_virtual = false,
919  },
920  {
921  .name = "g1",
922  .cls = &sparc_reg_classes[CLASS_sparc_gp],
923  .single_req = &sparc_single_reg_req_gp_g1,
924  .index = REG_GP_G1,
925  .global_index = REG_G1,
926  .dwarf_number = 1,
927  .encoding = 1,
928  .is_virtual = false,
929  },
930  {
931  .name = "g2",
932  .cls = &sparc_reg_classes[CLASS_sparc_gp],
933  .single_req = &sparc_single_reg_req_gp_g2,
934  .index = REG_GP_G2,
935  .global_index = REG_G2,
936  .dwarf_number = 2,
937  .encoding = 2,
938  .is_virtual = false,
939  },
940  {
941  .name = "g3",
942  .cls = &sparc_reg_classes[CLASS_sparc_gp],
943  .single_req = &sparc_single_reg_req_gp_g3,
944  .index = REG_GP_G3,
945  .global_index = REG_G3,
946  .dwarf_number = 3,
947  .encoding = 3,
948  .is_virtual = false,
949  },
950  {
951  .name = "g4",
952  .cls = &sparc_reg_classes[CLASS_sparc_gp],
953  .single_req = &sparc_single_reg_req_gp_g4,
954  .index = REG_GP_G4,
955  .global_index = REG_G4,
956  .dwarf_number = 4,
957  .encoding = 4,
958  .is_virtual = false,
959  },
960  {
961  .name = "g5",
962  .cls = &sparc_reg_classes[CLASS_sparc_gp],
963  .single_req = &sparc_single_reg_req_gp_g5,
964  .index = REG_GP_G5,
965  .global_index = REG_G5,
966  .dwarf_number = 5,
967  .encoding = 5,
968  .is_virtual = false,
969  },
970  {
971  .name = "g6",
972  .cls = &sparc_reg_classes[CLASS_sparc_gp],
973  .single_req = &sparc_single_reg_req_gp_g6,
974  .index = REG_GP_G6,
975  .global_index = REG_G6,
976  .dwarf_number = 6,
977  .encoding = 6,
978  .is_virtual = false,
979  },
980  {
981  .name = "g7",
982  .cls = &sparc_reg_classes[CLASS_sparc_gp],
983  .single_req = &sparc_single_reg_req_gp_g7,
984  .index = REG_GP_G7,
985  .global_index = REG_G7,
986  .dwarf_number = 7,
987  .encoding = 7,
988  .is_virtual = false,
989  },
990  {
991  .name = "o0",
992  .cls = &sparc_reg_classes[CLASS_sparc_gp],
993  .single_req = &sparc_single_reg_req_gp_o0,
994  .index = REG_GP_O0,
995  .global_index = REG_O0,
996  .dwarf_number = 8,
997  .encoding = 8,
998  .is_virtual = false,
999  },
1000  {
1001  .name = "o1",
1002  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1003  .single_req = &sparc_single_reg_req_gp_o1,
1004  .index = REG_GP_O1,
1005  .global_index = REG_O1,
1006  .dwarf_number = 9,
1007  .encoding = 9,
1008  .is_virtual = false,
1009  },
1010  {
1011  .name = "o2",
1012  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1013  .single_req = &sparc_single_reg_req_gp_o2,
1014  .index = REG_GP_O2,
1015  .global_index = REG_O2,
1016  .dwarf_number = 10,
1017  .encoding = 10,
1018  .is_virtual = false,
1019  },
1020  {
1021  .name = "o3",
1022  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1023  .single_req = &sparc_single_reg_req_gp_o3,
1024  .index = REG_GP_O3,
1025  .global_index = REG_O3,
1026  .dwarf_number = 11,
1027  .encoding = 11,
1028  .is_virtual = false,
1029  },
1030  {
1031  .name = "o4",
1032  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1033  .single_req = &sparc_single_reg_req_gp_o4,
1034  .index = REG_GP_O4,
1035  .global_index = REG_O4,
1036  .dwarf_number = 12,
1037  .encoding = 12,
1038  .is_virtual = false,
1039  },
1040  {
1041  .name = "o5",
1042  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1043  .single_req = &sparc_single_reg_req_gp_o5,
1044  .index = REG_GP_O5,
1045  .global_index = REG_O5,
1046  .dwarf_number = 13,
1047  .encoding = 13,
1048  .is_virtual = false,
1049  },
1050  {
1051  .name = "sp",
1052  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1053  .single_req = &sparc_single_reg_req_gp_sp,
1054  .index = REG_GP_SP,
1055  .global_index = REG_SP,
1056  .dwarf_number = 14,
1057  .encoding = 14,
1058  .is_virtual = false,
1059  },
1060  {
1061  .name = "o7",
1062  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1063  .single_req = &sparc_single_reg_req_gp_o7,
1064  .index = REG_GP_O7,
1065  .global_index = REG_O7,
1066  .dwarf_number = 15,
1067  .encoding = 15,
1068  .is_virtual = false,
1069  },
1070  {
1071  .name = "i0",
1072  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1073  .single_req = &sparc_single_reg_req_gp_i0,
1074  .index = REG_GP_I0,
1075  .global_index = REG_I0,
1076  .dwarf_number = 24,
1077  .encoding = 24,
1078  .is_virtual = false,
1079  },
1080  {
1081  .name = "i1",
1082  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1083  .single_req = &sparc_single_reg_req_gp_i1,
1084  .index = REG_GP_I1,
1085  .global_index = REG_I1,
1086  .dwarf_number = 25,
1087  .encoding = 25,
1088  .is_virtual = false,
1089  },
1090  {
1091  .name = "i2",
1092  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1093  .single_req = &sparc_single_reg_req_gp_i2,
1094  .index = REG_GP_I2,
1095  .global_index = REG_I2,
1096  .dwarf_number = 26,
1097  .encoding = 26,
1098  .is_virtual = false,
1099  },
1100  {
1101  .name = "i3",
1102  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1103  .single_req = &sparc_single_reg_req_gp_i3,
1104  .index = REG_GP_I3,
1105  .global_index = REG_I3,
1106  .dwarf_number = 27,
1107  .encoding = 27,
1108  .is_virtual = false,
1109  },
1110  {
1111  .name = "i4",
1112  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1113  .single_req = &sparc_single_reg_req_gp_i4,
1114  .index = REG_GP_I4,
1115  .global_index = REG_I4,
1116  .dwarf_number = 28,
1117  .encoding = 28,
1118  .is_virtual = false,
1119  },
1120  {
1121  .name = "i5",
1122  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1123  .single_req = &sparc_single_reg_req_gp_i5,
1124  .index = REG_GP_I5,
1125  .global_index = REG_I5,
1126  .dwarf_number = 29,
1127  .encoding = 29,
1128  .is_virtual = false,
1129  },
1130  {
1131  .name = "fp",
1132  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1133  .single_req = &sparc_single_reg_req_gp_fp,
1134  .index = REG_GP_FP,
1135  .global_index = REG_FP,
1136  .dwarf_number = 30,
1137  .encoding = 30,
1138  .is_virtual = false,
1139  },
1140  {
1141  .name = "i7",
1142  .cls = &sparc_reg_classes[CLASS_sparc_gp],
1143  .single_req = &sparc_single_reg_req_gp_i7,
1144  .index = REG_GP_I7,
1145  .global_index = REG_I7,
1146  .dwarf_number = 31,
1147  .encoding = 31,
1148  .is_virtual = false,
1149  },
1150  {
1151  .name = "y",
1152  .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
1153  .single_req = &sparc_single_reg_req_mul_div_high_res_y,
1154  .index = REG_MUL_DIV_HIGH_RES_Y,
1155  .global_index = REG_Y,
1156  .dwarf_number = 0,
1157  .encoding = REG_MUL_DIV_HIGH_RES_Y,
1158  .is_virtual = false,
1159  },
1160 
1161 };
1162 
1166 void sparc_register_init(void)
1167 {
1168  sparc_reg_classes[CLASS_sparc_flags].mode = mode_Bu;
1169  sparc_reg_classes[CLASS_sparc_fp].mode = mode_F;
1170  sparc_reg_classes[CLASS_sparc_fpflags].mode = mode_Bu;
1171  sparc_reg_classes[CLASS_sparc_gp].mode = mode_Iu;
1172  sparc_reg_classes[CLASS_sparc_mul_div_high_res].mode = mode_Iu;
1173 
1174 }
ir_mode * mode_Bu
uint8
Definition: irmode.h:195
ir_mode * mode_Iu
uint32
Definition: irmode.h:199
ir_mode * mode_F
ieee754 binary32 float (single precision)
Definition: irmode.h:192