11 #include "gen_sparc_regalloc_if.h" 13 #include "sparc_bearch_t.h" 15 const arch_register_req_t sparc_class_reg_req_flags = {
16 .cls = &sparc_reg_classes[CLASS_sparc_flags],
19 static const unsigned sparc_limited_flags_psr[] = { (1U << REG_FLAGS_PSR) };
20 const arch_register_req_t sparc_single_reg_req_flags_psr = {
21 .cls = &sparc_reg_classes[CLASS_sparc_flags],
22 .limited = sparc_limited_flags_psr,
25 const arch_register_req_t sparc_class_reg_req_fp = {
26 .cls = &sparc_reg_classes[CLASS_sparc_fp],
29 static const unsigned sparc_limited_fp_f0[] = { (1U << REG_FP_F0), 0 };
30 const arch_register_req_t sparc_single_reg_req_fp_f0 = {
31 .cls = &sparc_reg_classes[CLASS_sparc_fp],
32 .limited = sparc_limited_fp_f0,
35 static const unsigned sparc_limited_fp_f1[] = { (1U << REG_FP_F1), 0 };
36 const arch_register_req_t sparc_single_reg_req_fp_f1 = {
37 .cls = &sparc_reg_classes[CLASS_sparc_fp],
38 .limited = sparc_limited_fp_f1,
41 static const unsigned sparc_limited_fp_f2[] = { (1U << REG_FP_F2), 0 };
42 const arch_register_req_t sparc_single_reg_req_fp_f2 = {
43 .cls = &sparc_reg_classes[CLASS_sparc_fp],
44 .limited = sparc_limited_fp_f2,
47 static const unsigned sparc_limited_fp_f3[] = { (1U << REG_FP_F3), 0 };
48 const arch_register_req_t sparc_single_reg_req_fp_f3 = {
49 .cls = &sparc_reg_classes[CLASS_sparc_fp],
50 .limited = sparc_limited_fp_f3,
53 static const unsigned sparc_limited_fp_f4[] = { (1U << REG_FP_F4), 0 };
54 const arch_register_req_t sparc_single_reg_req_fp_f4 = {
55 .cls = &sparc_reg_classes[CLASS_sparc_fp],
56 .limited = sparc_limited_fp_f4,
59 static const unsigned sparc_limited_fp_f5[] = { (1U << REG_FP_F5), 0 };
60 const arch_register_req_t sparc_single_reg_req_fp_f5 = {
61 .cls = &sparc_reg_classes[CLASS_sparc_fp],
62 .limited = sparc_limited_fp_f5,
65 static const unsigned sparc_limited_fp_f6[] = { (1U << REG_FP_F6), 0 };
66 const arch_register_req_t sparc_single_reg_req_fp_f6 = {
67 .cls = &sparc_reg_classes[CLASS_sparc_fp],
68 .limited = sparc_limited_fp_f6,
71 static const unsigned sparc_limited_fp_f7[] = { (1U << REG_FP_F7), 0 };
72 const arch_register_req_t sparc_single_reg_req_fp_f7 = {
73 .cls = &sparc_reg_classes[CLASS_sparc_fp],
74 .limited = sparc_limited_fp_f7,
77 static const unsigned sparc_limited_fp_f8[] = { (1U << REG_FP_F8), 0 };
78 const arch_register_req_t sparc_single_reg_req_fp_f8 = {
79 .cls = &sparc_reg_classes[CLASS_sparc_fp],
80 .limited = sparc_limited_fp_f8,
83 static const unsigned sparc_limited_fp_f9[] = { (1U << REG_FP_F9), 0 };
84 const arch_register_req_t sparc_single_reg_req_fp_f9 = {
85 .cls = &sparc_reg_classes[CLASS_sparc_fp],
86 .limited = sparc_limited_fp_f9,
89 static const unsigned sparc_limited_fp_f10[] = { (1U << REG_FP_F10), 0 };
90 const arch_register_req_t sparc_single_reg_req_fp_f10 = {
91 .cls = &sparc_reg_classes[CLASS_sparc_fp],
92 .limited = sparc_limited_fp_f10,
95 static const unsigned sparc_limited_fp_f11[] = { (1U << REG_FP_F11), 0 };
96 const arch_register_req_t sparc_single_reg_req_fp_f11 = {
97 .cls = &sparc_reg_classes[CLASS_sparc_fp],
98 .limited = sparc_limited_fp_f11,
101 static const unsigned sparc_limited_fp_f12[] = { (1U << REG_FP_F12), 0 };
102 const arch_register_req_t sparc_single_reg_req_fp_f12 = {
103 .cls = &sparc_reg_classes[CLASS_sparc_fp],
104 .limited = sparc_limited_fp_f12,
107 static const unsigned sparc_limited_fp_f13[] = { (1U << REG_FP_F13), 0 };
108 const arch_register_req_t sparc_single_reg_req_fp_f13 = {
109 .cls = &sparc_reg_classes[CLASS_sparc_fp],
110 .limited = sparc_limited_fp_f13,
113 static const unsigned sparc_limited_fp_f14[] = { (1U << REG_FP_F14), 0 };
114 const arch_register_req_t sparc_single_reg_req_fp_f14 = {
115 .cls = &sparc_reg_classes[CLASS_sparc_fp],
116 .limited = sparc_limited_fp_f14,
119 static const unsigned sparc_limited_fp_f15[] = { (1U << REG_FP_F15), 0 };
120 const arch_register_req_t sparc_single_reg_req_fp_f15 = {
121 .cls = &sparc_reg_classes[CLASS_sparc_fp],
122 .limited = sparc_limited_fp_f15,
125 static const unsigned sparc_limited_fp_f16[] = { (1U << REG_FP_F16), 0 };
126 const arch_register_req_t sparc_single_reg_req_fp_f16 = {
127 .cls = &sparc_reg_classes[CLASS_sparc_fp],
128 .limited = sparc_limited_fp_f16,
131 static const unsigned sparc_limited_fp_f17[] = { (1U << REG_FP_F17), 0 };
132 const arch_register_req_t sparc_single_reg_req_fp_f17 = {
133 .cls = &sparc_reg_classes[CLASS_sparc_fp],
134 .limited = sparc_limited_fp_f17,
137 static const unsigned sparc_limited_fp_f18[] = { (1U << REG_FP_F18), 0 };
138 const arch_register_req_t sparc_single_reg_req_fp_f18 = {
139 .cls = &sparc_reg_classes[CLASS_sparc_fp],
140 .limited = sparc_limited_fp_f18,
143 static const unsigned sparc_limited_fp_f19[] = { (1U << REG_FP_F19), 0 };
144 const arch_register_req_t sparc_single_reg_req_fp_f19 = {
145 .cls = &sparc_reg_classes[CLASS_sparc_fp],
146 .limited = sparc_limited_fp_f19,
149 static const unsigned sparc_limited_fp_f20[] = { (1U << REG_FP_F20), 0 };
150 const arch_register_req_t sparc_single_reg_req_fp_f20 = {
151 .cls = &sparc_reg_classes[CLASS_sparc_fp],
152 .limited = sparc_limited_fp_f20,
155 static const unsigned sparc_limited_fp_f21[] = { (1U << REG_FP_F21), 0 };
156 const arch_register_req_t sparc_single_reg_req_fp_f21 = {
157 .cls = &sparc_reg_classes[CLASS_sparc_fp],
158 .limited = sparc_limited_fp_f21,
161 static const unsigned sparc_limited_fp_f22[] = { (1U << REG_FP_F22), 0 };
162 const arch_register_req_t sparc_single_reg_req_fp_f22 = {
163 .cls = &sparc_reg_classes[CLASS_sparc_fp],
164 .limited = sparc_limited_fp_f22,
167 static const unsigned sparc_limited_fp_f23[] = { (1U << REG_FP_F23), 0 };
168 const arch_register_req_t sparc_single_reg_req_fp_f23 = {
169 .cls = &sparc_reg_classes[CLASS_sparc_fp],
170 .limited = sparc_limited_fp_f23,
173 static const unsigned sparc_limited_fp_f24[] = { (1U << REG_FP_F24), 0 };
174 const arch_register_req_t sparc_single_reg_req_fp_f24 = {
175 .cls = &sparc_reg_classes[CLASS_sparc_fp],
176 .limited = sparc_limited_fp_f24,
179 static const unsigned sparc_limited_fp_f25[] = { (1U << REG_FP_F25), 0 };
180 const arch_register_req_t sparc_single_reg_req_fp_f25 = {
181 .cls = &sparc_reg_classes[CLASS_sparc_fp],
182 .limited = sparc_limited_fp_f25,
185 static const unsigned sparc_limited_fp_f26[] = { (1U << REG_FP_F26), 0 };
186 const arch_register_req_t sparc_single_reg_req_fp_f26 = {
187 .cls = &sparc_reg_classes[CLASS_sparc_fp],
188 .limited = sparc_limited_fp_f26,
191 static const unsigned sparc_limited_fp_f27[] = { (1U << REG_FP_F27), 0 };
192 const arch_register_req_t sparc_single_reg_req_fp_f27 = {
193 .cls = &sparc_reg_classes[CLASS_sparc_fp],
194 .limited = sparc_limited_fp_f27,
197 static const unsigned sparc_limited_fp_f28[] = { (1U << REG_FP_F28), 0 };
198 const arch_register_req_t sparc_single_reg_req_fp_f28 = {
199 .cls = &sparc_reg_classes[CLASS_sparc_fp],
200 .limited = sparc_limited_fp_f28,
203 static const unsigned sparc_limited_fp_f29[] = { (1U << REG_FP_F29), 0 };
204 const arch_register_req_t sparc_single_reg_req_fp_f29 = {
205 .cls = &sparc_reg_classes[CLASS_sparc_fp],
206 .limited = sparc_limited_fp_f29,
209 static const unsigned sparc_limited_fp_f30[] = { (1U << REG_FP_F30), 0 };
210 const arch_register_req_t sparc_single_reg_req_fp_f30 = {
211 .cls = &sparc_reg_classes[CLASS_sparc_fp],
212 .limited = sparc_limited_fp_f30,
215 static const unsigned sparc_limited_fp_f31[] = { (1U << REG_FP_F31), 0 };
216 const arch_register_req_t sparc_single_reg_req_fp_f31 = {
217 .cls = &sparc_reg_classes[CLASS_sparc_fp],
218 .limited = sparc_limited_fp_f31,
221 const arch_register_req_t sparc_class_reg_req_fpflags = {
222 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
225 static const unsigned sparc_limited_fpflags_fsr[] = { (1U << REG_FPFLAGS_FSR) };
226 const arch_register_req_t sparc_single_reg_req_fpflags_fsr = {
227 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
228 .limited = sparc_limited_fpflags_fsr,
231 const arch_register_req_t sparc_class_reg_req_gp = {
232 .cls = &sparc_reg_classes[CLASS_sparc_gp],
235 static const unsigned sparc_limited_gp_l0[] = { (1U << REG_GP_L0), 0 };
236 const arch_register_req_t sparc_single_reg_req_gp_l0 = {
237 .cls = &sparc_reg_classes[CLASS_sparc_gp],
238 .limited = sparc_limited_gp_l0,
241 static const unsigned sparc_limited_gp_l1[] = { (1U << REG_GP_L1), 0 };
242 const arch_register_req_t sparc_single_reg_req_gp_l1 = {
243 .cls = &sparc_reg_classes[CLASS_sparc_gp],
244 .limited = sparc_limited_gp_l1,
247 static const unsigned sparc_limited_gp_l2[] = { (1U << REG_GP_L2), 0 };
248 const arch_register_req_t sparc_single_reg_req_gp_l2 = {
249 .cls = &sparc_reg_classes[CLASS_sparc_gp],
250 .limited = sparc_limited_gp_l2,
253 static const unsigned sparc_limited_gp_l3[] = { (1U << REG_GP_L3), 0 };
254 const arch_register_req_t sparc_single_reg_req_gp_l3 = {
255 .cls = &sparc_reg_classes[CLASS_sparc_gp],
256 .limited = sparc_limited_gp_l3,
259 static const unsigned sparc_limited_gp_l4[] = { (1U << REG_GP_L4), 0 };
260 const arch_register_req_t sparc_single_reg_req_gp_l4 = {
261 .cls = &sparc_reg_classes[CLASS_sparc_gp],
262 .limited = sparc_limited_gp_l4,
265 static const unsigned sparc_limited_gp_l5[] = { (1U << REG_GP_L5), 0 };
266 const arch_register_req_t sparc_single_reg_req_gp_l5 = {
267 .cls = &sparc_reg_classes[CLASS_sparc_gp],
268 .limited = sparc_limited_gp_l5,
271 static const unsigned sparc_limited_gp_l6[] = { (1U << REG_GP_L6), 0 };
272 const arch_register_req_t sparc_single_reg_req_gp_l6 = {
273 .cls = &sparc_reg_classes[CLASS_sparc_gp],
274 .limited = sparc_limited_gp_l6,
277 static const unsigned sparc_limited_gp_l7[] = { (1U << REG_GP_L7), 0 };
278 const arch_register_req_t sparc_single_reg_req_gp_l7 = {
279 .cls = &sparc_reg_classes[CLASS_sparc_gp],
280 .limited = sparc_limited_gp_l7,
283 static const unsigned sparc_limited_gp_g0[] = { (1U << REG_GP_G0), 0 };
284 const arch_register_req_t sparc_single_reg_req_gp_g0 = {
285 .cls = &sparc_reg_classes[CLASS_sparc_gp],
286 .limited = sparc_limited_gp_g0,
289 static const unsigned sparc_limited_gp_g1[] = { (1U << REG_GP_G1), 0 };
290 const arch_register_req_t sparc_single_reg_req_gp_g1 = {
291 .cls = &sparc_reg_classes[CLASS_sparc_gp],
292 .limited = sparc_limited_gp_g1,
295 static const unsigned sparc_limited_gp_g2[] = { (1U << REG_GP_G2), 0 };
296 const arch_register_req_t sparc_single_reg_req_gp_g2 = {
297 .cls = &sparc_reg_classes[CLASS_sparc_gp],
298 .limited = sparc_limited_gp_g2,
301 static const unsigned sparc_limited_gp_g3[] = { (1U << REG_GP_G3), 0 };
302 const arch_register_req_t sparc_single_reg_req_gp_g3 = {
303 .cls = &sparc_reg_classes[CLASS_sparc_gp],
304 .limited = sparc_limited_gp_g3,
307 static const unsigned sparc_limited_gp_g4[] = { (1U << REG_GP_G4), 0 };
308 const arch_register_req_t sparc_single_reg_req_gp_g4 = {
309 .cls = &sparc_reg_classes[CLASS_sparc_gp],
310 .limited = sparc_limited_gp_g4,
313 static const unsigned sparc_limited_gp_g5[] = { (1U << REG_GP_G5), 0 };
314 const arch_register_req_t sparc_single_reg_req_gp_g5 = {
315 .cls = &sparc_reg_classes[CLASS_sparc_gp],
316 .limited = sparc_limited_gp_g5,
319 static const unsigned sparc_limited_gp_g6[] = { (1U << REG_GP_G6), 0 };
320 const arch_register_req_t sparc_single_reg_req_gp_g6 = {
321 .cls = &sparc_reg_classes[CLASS_sparc_gp],
322 .limited = sparc_limited_gp_g6,
325 static const unsigned sparc_limited_gp_g7[] = { (1U << REG_GP_G7), 0 };
326 const arch_register_req_t sparc_single_reg_req_gp_g7 = {
327 .cls = &sparc_reg_classes[CLASS_sparc_gp],
328 .limited = sparc_limited_gp_g7,
331 static const unsigned sparc_limited_gp_o0[] = { (1U << REG_GP_O0), 0 };
332 const arch_register_req_t sparc_single_reg_req_gp_o0 = {
333 .cls = &sparc_reg_classes[CLASS_sparc_gp],
334 .limited = sparc_limited_gp_o0,
337 static const unsigned sparc_limited_gp_o1[] = { (1U << REG_GP_O1), 0 };
338 const arch_register_req_t sparc_single_reg_req_gp_o1 = {
339 .cls = &sparc_reg_classes[CLASS_sparc_gp],
340 .limited = sparc_limited_gp_o1,
343 static const unsigned sparc_limited_gp_o2[] = { (1U << REG_GP_O2), 0 };
344 const arch_register_req_t sparc_single_reg_req_gp_o2 = {
345 .cls = &sparc_reg_classes[CLASS_sparc_gp],
346 .limited = sparc_limited_gp_o2,
349 static const unsigned sparc_limited_gp_o3[] = { (1U << REG_GP_O3), 0 };
350 const arch_register_req_t sparc_single_reg_req_gp_o3 = {
351 .cls = &sparc_reg_classes[CLASS_sparc_gp],
352 .limited = sparc_limited_gp_o3,
355 static const unsigned sparc_limited_gp_o4[] = { (1U << REG_GP_O4), 0 };
356 const arch_register_req_t sparc_single_reg_req_gp_o4 = {
357 .cls = &sparc_reg_classes[CLASS_sparc_gp],
358 .limited = sparc_limited_gp_o4,
361 static const unsigned sparc_limited_gp_o5[] = { (1U << REG_GP_O5), 0 };
362 const arch_register_req_t sparc_single_reg_req_gp_o5 = {
363 .cls = &sparc_reg_classes[CLASS_sparc_gp],
364 .limited = sparc_limited_gp_o5,
367 static const unsigned sparc_limited_gp_sp[] = { (1U << REG_GP_SP), 0 };
368 const arch_register_req_t sparc_single_reg_req_gp_sp = {
369 .cls = &sparc_reg_classes[CLASS_sparc_gp],
370 .limited = sparc_limited_gp_sp,
373 static const unsigned sparc_limited_gp_o7[] = { (1U << REG_GP_O7), 0 };
374 const arch_register_req_t sparc_single_reg_req_gp_o7 = {
375 .cls = &sparc_reg_classes[CLASS_sparc_gp],
376 .limited = sparc_limited_gp_o7,
379 static const unsigned sparc_limited_gp_i0[] = { (1U << REG_GP_I0), 0 };
380 const arch_register_req_t sparc_single_reg_req_gp_i0 = {
381 .cls = &sparc_reg_classes[CLASS_sparc_gp],
382 .limited = sparc_limited_gp_i0,
385 static const unsigned sparc_limited_gp_i1[] = { (1U << REG_GP_I1), 0 };
386 const arch_register_req_t sparc_single_reg_req_gp_i1 = {
387 .cls = &sparc_reg_classes[CLASS_sparc_gp],
388 .limited = sparc_limited_gp_i1,
391 static const unsigned sparc_limited_gp_i2[] = { (1U << REG_GP_I2), 0 };
392 const arch_register_req_t sparc_single_reg_req_gp_i2 = {
393 .cls = &sparc_reg_classes[CLASS_sparc_gp],
394 .limited = sparc_limited_gp_i2,
397 static const unsigned sparc_limited_gp_i3[] = { (1U << REG_GP_I3), 0 };
398 const arch_register_req_t sparc_single_reg_req_gp_i3 = {
399 .cls = &sparc_reg_classes[CLASS_sparc_gp],
400 .limited = sparc_limited_gp_i3,
403 static const unsigned sparc_limited_gp_i4[] = { (1U << REG_GP_I4), 0 };
404 const arch_register_req_t sparc_single_reg_req_gp_i4 = {
405 .cls = &sparc_reg_classes[CLASS_sparc_gp],
406 .limited = sparc_limited_gp_i4,
409 static const unsigned sparc_limited_gp_i5[] = { (1U << REG_GP_I5), 0 };
410 const arch_register_req_t sparc_single_reg_req_gp_i5 = {
411 .cls = &sparc_reg_classes[CLASS_sparc_gp],
412 .limited = sparc_limited_gp_i5,
415 static const unsigned sparc_limited_gp_fp[] = { (1U << REG_GP_FP), 0 };
416 const arch_register_req_t sparc_single_reg_req_gp_fp = {
417 .cls = &sparc_reg_classes[CLASS_sparc_gp],
418 .limited = sparc_limited_gp_fp,
421 static const unsigned sparc_limited_gp_i7[] = { (1U << REG_GP_I7), 0 };
422 const arch_register_req_t sparc_single_reg_req_gp_i7 = {
423 .cls = &sparc_reg_classes[CLASS_sparc_gp],
424 .limited = sparc_limited_gp_i7,
427 const arch_register_req_t sparc_class_reg_req_mul_div_high_res = {
428 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
431 static const unsigned sparc_limited_mul_div_high_res_y[] = { (1U << REG_MUL_DIV_HIGH_RES_Y) };
432 const arch_register_req_t sparc_single_reg_req_mul_div_high_res_y = {
433 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
434 .limited = sparc_limited_mul_div_high_res_y,
439 arch_register_class_t sparc_reg_classes[] = {
441 .name =
"sparc_flags",
443 .regs = &sparc_registers[REG_PSR],
444 .class_req = &sparc_class_reg_req_flags,
445 .index = CLASS_sparc_flags,
452 .regs = &sparc_registers[REG_F0],
453 .class_req = &sparc_class_reg_req_fp,
454 .index = CLASS_sparc_fp,
459 .name =
"sparc_fpflags",
461 .regs = &sparc_registers[REG_FSR],
462 .class_req = &sparc_class_reg_req_fpflags,
463 .index = CLASS_sparc_fpflags,
470 .regs = &sparc_registers[REG_L0],
471 .class_req = &sparc_class_reg_req_gp,
472 .index = CLASS_sparc_gp,
477 .name =
"sparc_mul_div_high_res",
479 .regs = &sparc_registers[REG_Y],
480 .class_req = &sparc_class_reg_req_mul_div_high_res,
481 .index = CLASS_sparc_mul_div_high_res,
489 const arch_register_t sparc_registers[] = {
492 .cls = &sparc_reg_classes[CLASS_sparc_flags],
493 .single_req = &sparc_single_reg_req_flags_psr,
494 .index = REG_FLAGS_PSR,
495 .global_index = REG_PSR,
497 .encoding = REG_FLAGS_PSR,
502 .cls = &sparc_reg_classes[CLASS_sparc_fp],
503 .single_req = &sparc_single_reg_req_fp_f0,
505 .global_index = REG_F0,
512 .cls = &sparc_reg_classes[CLASS_sparc_fp],
513 .single_req = &sparc_single_reg_req_fp_f1,
515 .global_index = REG_F1,
522 .cls = &sparc_reg_classes[CLASS_sparc_fp],
523 .single_req = &sparc_single_reg_req_fp_f2,
525 .global_index = REG_F2,
532 .cls = &sparc_reg_classes[CLASS_sparc_fp],
533 .single_req = &sparc_single_reg_req_fp_f3,
535 .global_index = REG_F3,
542 .cls = &sparc_reg_classes[CLASS_sparc_fp],
543 .single_req = &sparc_single_reg_req_fp_f4,
545 .global_index = REG_F4,
552 .cls = &sparc_reg_classes[CLASS_sparc_fp],
553 .single_req = &sparc_single_reg_req_fp_f5,
555 .global_index = REG_F5,
562 .cls = &sparc_reg_classes[CLASS_sparc_fp],
563 .single_req = &sparc_single_reg_req_fp_f6,
565 .global_index = REG_F6,
572 .cls = &sparc_reg_classes[CLASS_sparc_fp],
573 .single_req = &sparc_single_reg_req_fp_f7,
575 .global_index = REG_F7,
582 .cls = &sparc_reg_classes[CLASS_sparc_fp],
583 .single_req = &sparc_single_reg_req_fp_f8,
585 .global_index = REG_F8,
592 .cls = &sparc_reg_classes[CLASS_sparc_fp],
593 .single_req = &sparc_single_reg_req_fp_f9,
595 .global_index = REG_F9,
602 .cls = &sparc_reg_classes[CLASS_sparc_fp],
603 .single_req = &sparc_single_reg_req_fp_f10,
605 .global_index = REG_F10,
612 .cls = &sparc_reg_classes[CLASS_sparc_fp],
613 .single_req = &sparc_single_reg_req_fp_f11,
615 .global_index = REG_F11,
622 .cls = &sparc_reg_classes[CLASS_sparc_fp],
623 .single_req = &sparc_single_reg_req_fp_f12,
625 .global_index = REG_F12,
632 .cls = &sparc_reg_classes[CLASS_sparc_fp],
633 .single_req = &sparc_single_reg_req_fp_f13,
635 .global_index = REG_F13,
642 .cls = &sparc_reg_classes[CLASS_sparc_fp],
643 .single_req = &sparc_single_reg_req_fp_f14,
645 .global_index = REG_F14,
652 .cls = &sparc_reg_classes[CLASS_sparc_fp],
653 .single_req = &sparc_single_reg_req_fp_f15,
655 .global_index = REG_F15,
662 .cls = &sparc_reg_classes[CLASS_sparc_fp],
663 .single_req = &sparc_single_reg_req_fp_f16,
665 .global_index = REG_F16,
672 .cls = &sparc_reg_classes[CLASS_sparc_fp],
673 .single_req = &sparc_single_reg_req_fp_f17,
675 .global_index = REG_F17,
682 .cls = &sparc_reg_classes[CLASS_sparc_fp],
683 .single_req = &sparc_single_reg_req_fp_f18,
685 .global_index = REG_F18,
692 .cls = &sparc_reg_classes[CLASS_sparc_fp],
693 .single_req = &sparc_single_reg_req_fp_f19,
695 .global_index = REG_F19,
702 .cls = &sparc_reg_classes[CLASS_sparc_fp],
703 .single_req = &sparc_single_reg_req_fp_f20,
705 .global_index = REG_F20,
712 .cls = &sparc_reg_classes[CLASS_sparc_fp],
713 .single_req = &sparc_single_reg_req_fp_f21,
715 .global_index = REG_F21,
722 .cls = &sparc_reg_classes[CLASS_sparc_fp],
723 .single_req = &sparc_single_reg_req_fp_f22,
725 .global_index = REG_F22,
732 .cls = &sparc_reg_classes[CLASS_sparc_fp],
733 .single_req = &sparc_single_reg_req_fp_f23,
735 .global_index = REG_F23,
742 .cls = &sparc_reg_classes[CLASS_sparc_fp],
743 .single_req = &sparc_single_reg_req_fp_f24,
745 .global_index = REG_F24,
752 .cls = &sparc_reg_classes[CLASS_sparc_fp],
753 .single_req = &sparc_single_reg_req_fp_f25,
755 .global_index = REG_F25,
762 .cls = &sparc_reg_classes[CLASS_sparc_fp],
763 .single_req = &sparc_single_reg_req_fp_f26,
765 .global_index = REG_F26,
772 .cls = &sparc_reg_classes[CLASS_sparc_fp],
773 .single_req = &sparc_single_reg_req_fp_f27,
775 .global_index = REG_F27,
782 .cls = &sparc_reg_classes[CLASS_sparc_fp],
783 .single_req = &sparc_single_reg_req_fp_f28,
785 .global_index = REG_F28,
792 .cls = &sparc_reg_classes[CLASS_sparc_fp],
793 .single_req = &sparc_single_reg_req_fp_f29,
795 .global_index = REG_F29,
802 .cls = &sparc_reg_classes[CLASS_sparc_fp],
803 .single_req = &sparc_single_reg_req_fp_f30,
805 .global_index = REG_F30,
812 .cls = &sparc_reg_classes[CLASS_sparc_fp],
813 .single_req = &sparc_single_reg_req_fp_f31,
815 .global_index = REG_F31,
822 .cls = &sparc_reg_classes[CLASS_sparc_fpflags],
823 .single_req = &sparc_single_reg_req_fpflags_fsr,
824 .index = REG_FPFLAGS_FSR,
825 .global_index = REG_FSR,
827 .encoding = REG_FPFLAGS_FSR,
832 .cls = &sparc_reg_classes[CLASS_sparc_gp],
833 .single_req = &sparc_single_reg_req_gp_l0,
835 .global_index = REG_L0,
842 .cls = &sparc_reg_classes[CLASS_sparc_gp],
843 .single_req = &sparc_single_reg_req_gp_l1,
845 .global_index = REG_L1,
852 .cls = &sparc_reg_classes[CLASS_sparc_gp],
853 .single_req = &sparc_single_reg_req_gp_l2,
855 .global_index = REG_L2,
862 .cls = &sparc_reg_classes[CLASS_sparc_gp],
863 .single_req = &sparc_single_reg_req_gp_l3,
865 .global_index = REG_L3,
872 .cls = &sparc_reg_classes[CLASS_sparc_gp],
873 .single_req = &sparc_single_reg_req_gp_l4,
875 .global_index = REG_L4,
882 .cls = &sparc_reg_classes[CLASS_sparc_gp],
883 .single_req = &sparc_single_reg_req_gp_l5,
885 .global_index = REG_L5,
892 .cls = &sparc_reg_classes[CLASS_sparc_gp],
893 .single_req = &sparc_single_reg_req_gp_l6,
895 .global_index = REG_L6,
902 .cls = &sparc_reg_classes[CLASS_sparc_gp],
903 .single_req = &sparc_single_reg_req_gp_l7,
905 .global_index = REG_L7,
912 .cls = &sparc_reg_classes[CLASS_sparc_gp],
913 .single_req = &sparc_single_reg_req_gp_g0,
915 .global_index = REG_G0,
922 .cls = &sparc_reg_classes[CLASS_sparc_gp],
923 .single_req = &sparc_single_reg_req_gp_g1,
925 .global_index = REG_G1,
932 .cls = &sparc_reg_classes[CLASS_sparc_gp],
933 .single_req = &sparc_single_reg_req_gp_g2,
935 .global_index = REG_G2,
942 .cls = &sparc_reg_classes[CLASS_sparc_gp],
943 .single_req = &sparc_single_reg_req_gp_g3,
945 .global_index = REG_G3,
952 .cls = &sparc_reg_classes[CLASS_sparc_gp],
953 .single_req = &sparc_single_reg_req_gp_g4,
955 .global_index = REG_G4,
962 .cls = &sparc_reg_classes[CLASS_sparc_gp],
963 .single_req = &sparc_single_reg_req_gp_g5,
965 .global_index = REG_G5,
972 .cls = &sparc_reg_classes[CLASS_sparc_gp],
973 .single_req = &sparc_single_reg_req_gp_g6,
975 .global_index = REG_G6,
982 .cls = &sparc_reg_classes[CLASS_sparc_gp],
983 .single_req = &sparc_single_reg_req_gp_g7,
985 .global_index = REG_G7,
992 .cls = &sparc_reg_classes[CLASS_sparc_gp],
993 .single_req = &sparc_single_reg_req_gp_o0,
995 .global_index = REG_O0,
1002 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1003 .single_req = &sparc_single_reg_req_gp_o1,
1005 .global_index = REG_O1,
1008 .is_virtual =
false,
1012 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1013 .single_req = &sparc_single_reg_req_gp_o2,
1015 .global_index = REG_O2,
1018 .is_virtual =
false,
1022 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1023 .single_req = &sparc_single_reg_req_gp_o3,
1025 .global_index = REG_O3,
1028 .is_virtual =
false,
1032 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1033 .single_req = &sparc_single_reg_req_gp_o4,
1035 .global_index = REG_O4,
1038 .is_virtual =
false,
1042 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1043 .single_req = &sparc_single_reg_req_gp_o5,
1045 .global_index = REG_O5,
1048 .is_virtual =
false,
1052 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1053 .single_req = &sparc_single_reg_req_gp_sp,
1055 .global_index = REG_SP,
1058 .is_virtual =
false,
1062 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1063 .single_req = &sparc_single_reg_req_gp_o7,
1065 .global_index = REG_O7,
1068 .is_virtual =
false,
1072 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1073 .single_req = &sparc_single_reg_req_gp_i0,
1075 .global_index = REG_I0,
1078 .is_virtual =
false,
1082 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1083 .single_req = &sparc_single_reg_req_gp_i1,
1085 .global_index = REG_I1,
1088 .is_virtual =
false,
1092 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1093 .single_req = &sparc_single_reg_req_gp_i2,
1095 .global_index = REG_I2,
1098 .is_virtual =
false,
1102 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1103 .single_req = &sparc_single_reg_req_gp_i3,
1105 .global_index = REG_I3,
1108 .is_virtual =
false,
1112 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1113 .single_req = &sparc_single_reg_req_gp_i4,
1115 .global_index = REG_I4,
1118 .is_virtual =
false,
1122 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1123 .single_req = &sparc_single_reg_req_gp_i5,
1125 .global_index = REG_I5,
1128 .is_virtual =
false,
1132 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1133 .single_req = &sparc_single_reg_req_gp_fp,
1135 .global_index = REG_FP,
1138 .is_virtual =
false,
1142 .cls = &sparc_reg_classes[CLASS_sparc_gp],
1143 .single_req = &sparc_single_reg_req_gp_i7,
1145 .global_index = REG_I7,
1148 .is_virtual =
false,
1152 .cls = &sparc_reg_classes[CLASS_sparc_mul_div_high_res],
1153 .single_req = &sparc_single_reg_req_mul_div_high_res_y,
1154 .index = REG_MUL_DIV_HIGH_RES_Y,
1155 .global_index = REG_Y,
1157 .encoding = REG_MUL_DIV_HIGH_RES_Y,
1158 .is_virtual =
false,
1166 void sparc_register_init(
void)
1168 sparc_reg_classes[CLASS_sparc_flags].mode =
mode_Bu;
1169 sparc_reg_classes[CLASS_sparc_fp].mode =
mode_F;
1170 sparc_reg_classes[CLASS_sparc_fpflags].mode =
mode_Bu;
1171 sparc_reg_classes[CLASS_sparc_gp].mode =
mode_Iu;
1172 sparc_reg_classes[CLASS_sparc_mul_div_high_res].mode =
mode_Iu;
ir_mode * mode_F
ieee754 binary32 float (single precision)