libFirm
gen_ia32_regalloc_if.c
1 
11 #include "gen_ia32_regalloc_if.h"
12 
13 #include "ia32_bearch_t.h"
14 
15 const arch_register_req_t ia32_class_reg_req_flags = {
16  .cls = &ia32_reg_classes[CLASS_ia32_flags],
17  .width = 1,
18 };
19 static const unsigned ia32_limited_flags_eflags[] = { (1U << REG_FLAGS_EFLAGS) };
20 const arch_register_req_t ia32_single_reg_req_flags_eflags = {
21  .cls = &ia32_reg_classes[CLASS_ia32_flags],
22  .limited = ia32_limited_flags_eflags,
23  .width = 1,
24 };
25 const arch_register_req_t ia32_class_reg_req_fp = {
26  .cls = &ia32_reg_classes[CLASS_ia32_fp],
27  .width = 1,
28 };
29 static const unsigned ia32_limited_fp_st0[] = { (1U << REG_FP_ST0) };
30 const arch_register_req_t ia32_single_reg_req_fp_st0 = {
31  .cls = &ia32_reg_classes[CLASS_ia32_fp],
32  .limited = ia32_limited_fp_st0,
33  .width = 1,
34 };
35 static const unsigned ia32_limited_fp_st1[] = { (1U << REG_FP_ST1) };
36 const arch_register_req_t ia32_single_reg_req_fp_st1 = {
37  .cls = &ia32_reg_classes[CLASS_ia32_fp],
38  .limited = ia32_limited_fp_st1,
39  .width = 1,
40 };
41 static const unsigned ia32_limited_fp_st2[] = { (1U << REG_FP_ST2) };
42 const arch_register_req_t ia32_single_reg_req_fp_st2 = {
43  .cls = &ia32_reg_classes[CLASS_ia32_fp],
44  .limited = ia32_limited_fp_st2,
45  .width = 1,
46 };
47 static const unsigned ia32_limited_fp_st3[] = { (1U << REG_FP_ST3) };
48 const arch_register_req_t ia32_single_reg_req_fp_st3 = {
49  .cls = &ia32_reg_classes[CLASS_ia32_fp],
50  .limited = ia32_limited_fp_st3,
51  .width = 1,
52 };
53 static const unsigned ia32_limited_fp_st4[] = { (1U << REG_FP_ST4) };
54 const arch_register_req_t ia32_single_reg_req_fp_st4 = {
55  .cls = &ia32_reg_classes[CLASS_ia32_fp],
56  .limited = ia32_limited_fp_st4,
57  .width = 1,
58 };
59 static const unsigned ia32_limited_fp_st5[] = { (1U << REG_FP_ST5) };
60 const arch_register_req_t ia32_single_reg_req_fp_st5 = {
61  .cls = &ia32_reg_classes[CLASS_ia32_fp],
62  .limited = ia32_limited_fp_st5,
63  .width = 1,
64 };
65 static const unsigned ia32_limited_fp_st6[] = { (1U << REG_FP_ST6) };
66 const arch_register_req_t ia32_single_reg_req_fp_st6 = {
67  .cls = &ia32_reg_classes[CLASS_ia32_fp],
68  .limited = ia32_limited_fp_st6,
69  .width = 1,
70 };
71 static const unsigned ia32_limited_fp_st7[] = { (1U << REG_FP_ST7) };
72 const arch_register_req_t ia32_single_reg_req_fp_st7 = {
73  .cls = &ia32_reg_classes[CLASS_ia32_fp],
74  .limited = ia32_limited_fp_st7,
75  .width = 1,
76 };
77 static const unsigned ia32_limited_fp_fp_NOREG[] = { (1U << REG_FP_FP_NOREG) };
78 const arch_register_req_t ia32_single_reg_req_fp_fp_NOREG = {
79  .cls = &ia32_reg_classes[CLASS_ia32_fp],
80  .limited = ia32_limited_fp_fp_NOREG,
81  .width = 1,
82 };
83 const arch_register_req_t ia32_class_reg_req_fp_cw = {
84  .cls = &ia32_reg_classes[CLASS_ia32_fp_cw],
85  .width = 1,
86 };
87 static const unsigned ia32_limited_fp_cw_fpcw[] = { (1U << REG_FP_CW_FPCW) };
88 const arch_register_req_t ia32_single_reg_req_fp_cw_fpcw = {
89  .cls = &ia32_reg_classes[CLASS_ia32_fp_cw],
90  .limited = ia32_limited_fp_cw_fpcw,
91  .width = 1,
92 };
93 const arch_register_req_t ia32_class_reg_req_gp = {
94  .cls = &ia32_reg_classes[CLASS_ia32_gp],
95  .width = 1,
96 };
97 static const unsigned ia32_limited_gp_edx[] = { (1U << REG_GP_EDX) };
98 const arch_register_req_t ia32_single_reg_req_gp_edx = {
99  .cls = &ia32_reg_classes[CLASS_ia32_gp],
100  .limited = ia32_limited_gp_edx,
101  .width = 1,
102 };
103 static const unsigned ia32_limited_gp_ecx[] = { (1U << REG_GP_ECX) };
104 const arch_register_req_t ia32_single_reg_req_gp_ecx = {
105  .cls = &ia32_reg_classes[CLASS_ia32_gp],
106  .limited = ia32_limited_gp_ecx,
107  .width = 1,
108 };
109 static const unsigned ia32_limited_gp_eax[] = { (1U << REG_GP_EAX) };
110 const arch_register_req_t ia32_single_reg_req_gp_eax = {
111  .cls = &ia32_reg_classes[CLASS_ia32_gp],
112  .limited = ia32_limited_gp_eax,
113  .width = 1,
114 };
115 static const unsigned ia32_limited_gp_ebx[] = { (1U << REG_GP_EBX) };
116 const arch_register_req_t ia32_single_reg_req_gp_ebx = {
117  .cls = &ia32_reg_classes[CLASS_ia32_gp],
118  .limited = ia32_limited_gp_ebx,
119  .width = 1,
120 };
121 static const unsigned ia32_limited_gp_esi[] = { (1U << REG_GP_ESI) };
122 const arch_register_req_t ia32_single_reg_req_gp_esi = {
123  .cls = &ia32_reg_classes[CLASS_ia32_gp],
124  .limited = ia32_limited_gp_esi,
125  .width = 1,
126 };
127 static const unsigned ia32_limited_gp_edi[] = { (1U << REG_GP_EDI) };
128 const arch_register_req_t ia32_single_reg_req_gp_edi = {
129  .cls = &ia32_reg_classes[CLASS_ia32_gp],
130  .limited = ia32_limited_gp_edi,
131  .width = 1,
132 };
133 static const unsigned ia32_limited_gp_ebp[] = { (1U << REG_GP_EBP) };
134 const arch_register_req_t ia32_single_reg_req_gp_ebp = {
135  .cls = &ia32_reg_classes[CLASS_ia32_gp],
136  .limited = ia32_limited_gp_ebp,
137  .width = 1,
138 };
139 static const unsigned ia32_limited_gp_esp[] = { (1U << REG_GP_ESP) };
140 const arch_register_req_t ia32_single_reg_req_gp_esp = {
141  .cls = &ia32_reg_classes[CLASS_ia32_gp],
142  .limited = ia32_limited_gp_esp,
143  .width = 1,
144 };
145 static const unsigned ia32_limited_gp_gp_NOREG[] = { (1U << REG_GP_GP_NOREG) };
146 const arch_register_req_t ia32_single_reg_req_gp_gp_NOREG = {
147  .cls = &ia32_reg_classes[CLASS_ia32_gp],
148  .limited = ia32_limited_gp_gp_NOREG,
149  .width = 1,
150 };
151 const arch_register_req_t ia32_class_reg_req_xmm = {
152  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
153  .width = 1,
154 };
155 static const unsigned ia32_limited_xmm_xmm0[] = { (1U << REG_XMM_XMM0) };
156 const arch_register_req_t ia32_single_reg_req_xmm_xmm0 = {
157  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
158  .limited = ia32_limited_xmm_xmm0,
159  .width = 1,
160 };
161 static const unsigned ia32_limited_xmm_xmm1[] = { (1U << REG_XMM_XMM1) };
162 const arch_register_req_t ia32_single_reg_req_xmm_xmm1 = {
163  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
164  .limited = ia32_limited_xmm_xmm1,
165  .width = 1,
166 };
167 static const unsigned ia32_limited_xmm_xmm2[] = { (1U << REG_XMM_XMM2) };
168 const arch_register_req_t ia32_single_reg_req_xmm_xmm2 = {
169  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
170  .limited = ia32_limited_xmm_xmm2,
171  .width = 1,
172 };
173 static const unsigned ia32_limited_xmm_xmm3[] = { (1U << REG_XMM_XMM3) };
174 const arch_register_req_t ia32_single_reg_req_xmm_xmm3 = {
175  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
176  .limited = ia32_limited_xmm_xmm3,
177  .width = 1,
178 };
179 static const unsigned ia32_limited_xmm_xmm4[] = { (1U << REG_XMM_XMM4) };
180 const arch_register_req_t ia32_single_reg_req_xmm_xmm4 = {
181  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
182  .limited = ia32_limited_xmm_xmm4,
183  .width = 1,
184 };
185 static const unsigned ia32_limited_xmm_xmm5[] = { (1U << REG_XMM_XMM5) };
186 const arch_register_req_t ia32_single_reg_req_xmm_xmm5 = {
187  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
188  .limited = ia32_limited_xmm_xmm5,
189  .width = 1,
190 };
191 static const unsigned ia32_limited_xmm_xmm6[] = { (1U << REG_XMM_XMM6) };
192 const arch_register_req_t ia32_single_reg_req_xmm_xmm6 = {
193  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
194  .limited = ia32_limited_xmm_xmm6,
195  .width = 1,
196 };
197 static const unsigned ia32_limited_xmm_xmm7[] = { (1U << REG_XMM_XMM7) };
198 const arch_register_req_t ia32_single_reg_req_xmm_xmm7 = {
199  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
200  .limited = ia32_limited_xmm_xmm7,
201  .width = 1,
202 };
203 static const unsigned ia32_limited_xmm_xmm_NOREG[] = { (1U << REG_XMM_XMM_NOREG) };
204 const arch_register_req_t ia32_single_reg_req_xmm_xmm_NOREG = {
205  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
206  .limited = ia32_limited_xmm_xmm_NOREG,
207  .width = 1,
208 };
209 
210 
211 arch_register_class_t ia32_reg_classes[] = {
212  {
213  .name = "ia32_flags",
214  .mode = NULL,
215  .regs = &ia32_registers[REG_EFLAGS],
216  .class_req = &ia32_class_reg_req_flags,
217  .index = CLASS_ia32_flags,
218  .n_regs = 1,
219  .manual_ra = true,
220  },
221  {
222  .name = "ia32_fp",
223  .mode = NULL,
224  .regs = &ia32_registers[REG_ST0],
225  .class_req = &ia32_class_reg_req_fp,
226  .index = CLASS_ia32_fp,
227  .n_regs = 9,
228  .manual_ra = false,
229  },
230  {
231  .name = "ia32_fp_cw",
232  .mode = NULL,
233  .regs = &ia32_registers[REG_FPCW],
234  .class_req = &ia32_class_reg_req_fp_cw,
235  .index = CLASS_ia32_fp_cw,
236  .n_regs = 1,
237  .manual_ra = true,
238  },
239  {
240  .name = "ia32_gp",
241  .mode = NULL,
242  .regs = &ia32_registers[REG_EDX],
243  .class_req = &ia32_class_reg_req_gp,
244  .index = CLASS_ia32_gp,
245  .n_regs = 9,
246  .manual_ra = false,
247  },
248  {
249  .name = "ia32_xmm",
250  .mode = NULL,
251  .regs = &ia32_registers[REG_XMM0],
252  .class_req = &ia32_class_reg_req_xmm,
253  .index = CLASS_ia32_xmm,
254  .n_regs = 9,
255  .manual_ra = false,
256  },
257 
258 };
259 
261 const arch_register_t ia32_registers[] = {
262  {
263  .name = "eflags",
264  .cls = &ia32_reg_classes[CLASS_ia32_flags],
265  .single_req = &ia32_single_reg_req_flags_eflags,
266  .index = REG_FLAGS_EFLAGS,
267  .global_index = REG_EFLAGS,
268  .dwarf_number = 9,
269  .encoding = REG_FLAGS_EFLAGS,
270  .is_virtual = false,
271  },
272  {
273  .name = "st",
274  .cls = &ia32_reg_classes[CLASS_ia32_fp],
275  .single_req = &ia32_single_reg_req_fp_st0,
276  .index = REG_FP_ST0,
277  .global_index = REG_ST0,
278  .dwarf_number = 11,
279  .encoding = 0,
280  .is_virtual = false,
281  },
282  {
283  .name = "st(1)",
284  .cls = &ia32_reg_classes[CLASS_ia32_fp],
285  .single_req = &ia32_single_reg_req_fp_st1,
286  .index = REG_FP_ST1,
287  .global_index = REG_ST1,
288  .dwarf_number = 12,
289  .encoding = 1,
290  .is_virtual = false,
291  },
292  {
293  .name = "st(2)",
294  .cls = &ia32_reg_classes[CLASS_ia32_fp],
295  .single_req = &ia32_single_reg_req_fp_st2,
296  .index = REG_FP_ST2,
297  .global_index = REG_ST2,
298  .dwarf_number = 13,
299  .encoding = 2,
300  .is_virtual = false,
301  },
302  {
303  .name = "st(3)",
304  .cls = &ia32_reg_classes[CLASS_ia32_fp],
305  .single_req = &ia32_single_reg_req_fp_st3,
306  .index = REG_FP_ST3,
307  .global_index = REG_ST3,
308  .dwarf_number = 14,
309  .encoding = 3,
310  .is_virtual = false,
311  },
312  {
313  .name = "st(4)",
314  .cls = &ia32_reg_classes[CLASS_ia32_fp],
315  .single_req = &ia32_single_reg_req_fp_st4,
316  .index = REG_FP_ST4,
317  .global_index = REG_ST4,
318  .dwarf_number = 15,
319  .encoding = 4,
320  .is_virtual = false,
321  },
322  {
323  .name = "st(5)",
324  .cls = &ia32_reg_classes[CLASS_ia32_fp],
325  .single_req = &ia32_single_reg_req_fp_st5,
326  .index = REG_FP_ST5,
327  .global_index = REG_ST5,
328  .dwarf_number = 16,
329  .encoding = 5,
330  .is_virtual = false,
331  },
332  {
333  .name = "st(6)",
334  .cls = &ia32_reg_classes[CLASS_ia32_fp],
335  .single_req = &ia32_single_reg_req_fp_st6,
336  .index = REG_FP_ST6,
337  .global_index = REG_ST6,
338  .dwarf_number = 17,
339  .encoding = 6,
340  .is_virtual = false,
341  },
342  {
343  .name = "st(7)",
344  .cls = &ia32_reg_classes[CLASS_ia32_fp],
345  .single_req = &ia32_single_reg_req_fp_st7,
346  .index = REG_FP_ST7,
347  .global_index = REG_ST7,
348  .dwarf_number = 18,
349  .encoding = 7,
350  .is_virtual = false,
351  },
352  {
353  .name = "fp_NOREG",
354  .cls = &ia32_reg_classes[CLASS_ia32_fp],
355  .single_req = &ia32_single_reg_req_fp_fp_NOREG,
356  .index = REG_FP_FP_NOREG,
357  .global_index = REG_FP_NOREG,
358  .dwarf_number = 0,
359  .encoding = REG_FP_FP_NOREG,
360  .is_virtual = true,
361  },
362  {
363  .name = "fpcw",
364  .cls = &ia32_reg_classes[CLASS_ia32_fp_cw],
365  .single_req = &ia32_single_reg_req_fp_cw_fpcw,
366  .index = REG_FP_CW_FPCW,
367  .global_index = REG_FPCW,
368  .dwarf_number = 37,
369  .encoding = REG_FP_CW_FPCW,
370  .is_virtual = false,
371  },
372  {
373  .name = "edx",
374  .cls = &ia32_reg_classes[CLASS_ia32_gp],
375  .single_req = &ia32_single_reg_req_gp_edx,
376  .index = REG_GP_EDX,
377  .global_index = REG_EDX,
378  .dwarf_number = 2,
379  .encoding = 2,
380  .is_virtual = false,
381  },
382  {
383  .name = "ecx",
384  .cls = &ia32_reg_classes[CLASS_ia32_gp],
385  .single_req = &ia32_single_reg_req_gp_ecx,
386  .index = REG_GP_ECX,
387  .global_index = REG_ECX,
388  .dwarf_number = 1,
389  .encoding = 1,
390  .is_virtual = false,
391  },
392  {
393  .name = "eax",
394  .cls = &ia32_reg_classes[CLASS_ia32_gp],
395  .single_req = &ia32_single_reg_req_gp_eax,
396  .index = REG_GP_EAX,
397  .global_index = REG_EAX,
398  .dwarf_number = 0,
399  .encoding = 0,
400  .is_virtual = false,
401  },
402  {
403  .name = "ebx",
404  .cls = &ia32_reg_classes[CLASS_ia32_gp],
405  .single_req = &ia32_single_reg_req_gp_ebx,
406  .index = REG_GP_EBX,
407  .global_index = REG_EBX,
408  .dwarf_number = 3,
409  .encoding = 3,
410  .is_virtual = false,
411  },
412  {
413  .name = "esi",
414  .cls = &ia32_reg_classes[CLASS_ia32_gp],
415  .single_req = &ia32_single_reg_req_gp_esi,
416  .index = REG_GP_ESI,
417  .global_index = REG_ESI,
418  .dwarf_number = 6,
419  .encoding = 6,
420  .is_virtual = false,
421  },
422  {
423  .name = "edi",
424  .cls = &ia32_reg_classes[CLASS_ia32_gp],
425  .single_req = &ia32_single_reg_req_gp_edi,
426  .index = REG_GP_EDI,
427  .global_index = REG_EDI,
428  .dwarf_number = 7,
429  .encoding = 7,
430  .is_virtual = false,
431  },
432  {
433  .name = "ebp",
434  .cls = &ia32_reg_classes[CLASS_ia32_gp],
435  .single_req = &ia32_single_reg_req_gp_ebp,
436  .index = REG_GP_EBP,
437  .global_index = REG_EBP,
438  .dwarf_number = 5,
439  .encoding = 5,
440  .is_virtual = false,
441  },
442  {
443  .name = "esp",
444  .cls = &ia32_reg_classes[CLASS_ia32_gp],
445  .single_req = &ia32_single_reg_req_gp_esp,
446  .index = REG_GP_ESP,
447  .global_index = REG_ESP,
448  .dwarf_number = 4,
449  .encoding = 4,
450  .is_virtual = false,
451  },
452  {
453  .name = "gp_NOREG",
454  .cls = &ia32_reg_classes[CLASS_ia32_gp],
455  .single_req = &ia32_single_reg_req_gp_gp_NOREG,
456  .index = REG_GP_GP_NOREG,
457  .global_index = REG_GP_NOREG,
458  .dwarf_number = 0,
459  .encoding = REG_GP_GP_NOREG,
460  .is_virtual = true,
461  },
462  {
463  .name = "xmm0",
464  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
465  .single_req = &ia32_single_reg_req_xmm_xmm0,
466  .index = REG_XMM_XMM0,
467  .global_index = REG_XMM0,
468  .dwarf_number = 21,
469  .encoding = REG_XMM_XMM0,
470  .is_virtual = false,
471  },
472  {
473  .name = "xmm1",
474  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
475  .single_req = &ia32_single_reg_req_xmm_xmm1,
476  .index = REG_XMM_XMM1,
477  .global_index = REG_XMM1,
478  .dwarf_number = 22,
479  .encoding = REG_XMM_XMM1,
480  .is_virtual = false,
481  },
482  {
483  .name = "xmm2",
484  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
485  .single_req = &ia32_single_reg_req_xmm_xmm2,
486  .index = REG_XMM_XMM2,
487  .global_index = REG_XMM2,
488  .dwarf_number = 23,
489  .encoding = REG_XMM_XMM2,
490  .is_virtual = false,
491  },
492  {
493  .name = "xmm3",
494  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
495  .single_req = &ia32_single_reg_req_xmm_xmm3,
496  .index = REG_XMM_XMM3,
497  .global_index = REG_XMM3,
498  .dwarf_number = 24,
499  .encoding = REG_XMM_XMM3,
500  .is_virtual = false,
501  },
502  {
503  .name = "xmm4",
504  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
505  .single_req = &ia32_single_reg_req_xmm_xmm4,
506  .index = REG_XMM_XMM4,
507  .global_index = REG_XMM4,
508  .dwarf_number = 25,
509  .encoding = REG_XMM_XMM4,
510  .is_virtual = false,
511  },
512  {
513  .name = "xmm5",
514  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
515  .single_req = &ia32_single_reg_req_xmm_xmm5,
516  .index = REG_XMM_XMM5,
517  .global_index = REG_XMM5,
518  .dwarf_number = 26,
519  .encoding = REG_XMM_XMM5,
520  .is_virtual = false,
521  },
522  {
523  .name = "xmm6",
524  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
525  .single_req = &ia32_single_reg_req_xmm_xmm6,
526  .index = REG_XMM_XMM6,
527  .global_index = REG_XMM6,
528  .dwarf_number = 27,
529  .encoding = REG_XMM_XMM6,
530  .is_virtual = false,
531  },
532  {
533  .name = "xmm7",
534  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
535  .single_req = &ia32_single_reg_req_xmm_xmm7,
536  .index = REG_XMM_XMM7,
537  .global_index = REG_XMM7,
538  .dwarf_number = 28,
539  .encoding = REG_XMM_XMM7,
540  .is_virtual = false,
541  },
542  {
543  .name = "xmm_NOREG",
544  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
545  .single_req = &ia32_single_reg_req_xmm_xmm_NOREG,
546  .index = REG_XMM_XMM_NOREG,
547  .global_index = REG_XMM_NOREG,
548  .dwarf_number = 0,
549  .encoding = REG_XMM_XMM_NOREG,
550  .is_virtual = true,
551  },
552 
553 };
554 
558 void ia32_register_init(void)
559 {
560  ia32_reg_classes[CLASS_ia32_flags].mode = ia32_mode_flags;
561  ia32_reg_classes[CLASS_ia32_fp].mode = x86_mode_E;
562  ia32_reg_classes[CLASS_ia32_fp_cw].mode = ia32_mode_fpcw;
563  ia32_reg_classes[CLASS_ia32_gp].mode = ia32_mode_gp;
564  ia32_reg_classes[CLASS_ia32_xmm].mode = ia32_mode_float64;
565 
566 }