libFirm
gen_ia32_new_nodes.c
1 #include "gen_ia32_new_nodes.h"
2 
3 #include "benode.h"
4 #include "ia32_bearch_t.h"
5 #include "gen_ia32_regalloc_if.h"
6 #include "ia32_new_nodes_t.h"
7 #include "fourcc.h"
8 #include "irgopt.h"
9 #include "ircons_t.h"
10 
11 ir_op *op_ia32_Adc = NULL;
12 ir_op *op_ia32_Add = NULL;
13 ir_op *op_ia32_AddMem = NULL;
14 ir_op *op_ia32_AddSP = NULL;
15 ir_op *op_ia32_Adds = NULL;
16 ir_op *op_ia32_And = NULL;
17 ir_op *op_ia32_AndMem = NULL;
18 ir_op *op_ia32_Andnp = NULL;
19 ir_op *op_ia32_Andp = NULL;
20 ir_op *op_ia32_Breakpoint = NULL;
21 ir_op *op_ia32_Bsf = NULL;
22 ir_op *op_ia32_Bsr = NULL;
23 ir_op *op_ia32_Bswap = NULL;
24 ir_op *op_ia32_Bswap16 = NULL;
25 ir_op *op_ia32_Bt = NULL;
26 ir_op *op_ia32_CMovcc = NULL;
27 ir_op *op_ia32_Call = NULL;
28 ir_op *op_ia32_ChangeCW = NULL;
29 ir_op *op_ia32_Cltd = NULL;
30 ir_op *op_ia32_Cmc = NULL;
31 ir_op *op_ia32_Cmp = NULL;
32 ir_op *op_ia32_CmpXChgMem = NULL;
33 ir_op *op_ia32_Const = NULL;
34 ir_op *op_ia32_Conv_FP2FP = NULL;
35 ir_op *op_ia32_Conv_FP2I = NULL;
36 ir_op *op_ia32_Conv_I2FP = NULL;
37 ir_op *op_ia32_Conv_I2I = NULL;
38 ir_op *op_ia32_CopyB = NULL;
39 ir_op *op_ia32_CopyB_i = NULL;
40 ir_op *op_ia32_CopyEbpEsp = NULL;
41 ir_op *op_ia32_CvtSI2SD = NULL;
42 ir_op *op_ia32_CvtSI2SS = NULL;
43 ir_op *op_ia32_Cwtl = NULL;
44 ir_op *op_ia32_Dec = NULL;
45 ir_op *op_ia32_DecMem = NULL;
46 ir_op *op_ia32_Div = NULL;
47 ir_op *op_ia32_Divs = NULL;
48 ir_op *op_ia32_Enter = NULL;
49 ir_op *op_ia32_FldCW = NULL;
50 ir_op *op_ia32_FnstCW = NULL;
51 ir_op *op_ia32_FnstCWNOP = NULL;
52 ir_op *op_ia32_FtstFnstsw = NULL;
53 ir_op *op_ia32_FucomFnstsw = NULL;
54 ir_op *op_ia32_Fucomi = NULL;
55 ir_op *op_ia32_FucomppFnstsw = NULL;
56 ir_op *op_ia32_GetEIP = NULL;
57 ir_op *op_ia32_IDiv = NULL;
58 ir_op *op_ia32_IJmp = NULL;
59 ir_op *op_ia32_IMul = NULL;
60 ir_op *op_ia32_IMul1OP = NULL;
61 ir_op *op_ia32_IMulImm = NULL;
62 ir_op *op_ia32_Immediate = NULL;
63 ir_op *op_ia32_Inc = NULL;
64 ir_op *op_ia32_IncMem = NULL;
65 ir_op *op_ia32_Inport = NULL;
66 ir_op *op_ia32_Jcc = NULL;
67 ir_op *op_ia32_Jmp = NULL;
68 ir_op *op_ia32_LdTls = NULL;
69 ir_op *op_ia32_Lea = NULL;
70 ir_op *op_ia32_Leave = NULL;
71 ir_op *op_ia32_Load = NULL;
72 ir_op *op_ia32_Maxs = NULL;
73 ir_op *op_ia32_Mins = NULL;
74 ir_op *op_ia32_Minus64 = NULL;
75 ir_op *op_ia32_Movd = NULL;
76 ir_op *op_ia32_Mul = NULL;
77 ir_op *op_ia32_Muls = NULL;
78 ir_op *op_ia32_Neg = NULL;
79 ir_op *op_ia32_NegMem = NULL;
80 ir_op *op_ia32_NoReg_FP = NULL;
81 ir_op *op_ia32_NoReg_GP = NULL;
82 ir_op *op_ia32_NoReg_XMM = NULL;
83 ir_op *op_ia32_Not = NULL;
84 ir_op *op_ia32_NotMem = NULL;
85 ir_op *op_ia32_Or = NULL;
86 ir_op *op_ia32_OrMem = NULL;
87 ir_op *op_ia32_Orp = NULL;
88 ir_op *op_ia32_Outport = NULL;
89 ir_op *op_ia32_Pop = NULL;
90 ir_op *op_ia32_PopMem = NULL;
91 ir_op *op_ia32_Popcnt = NULL;
92 ir_op *op_ia32_Prefetch = NULL;
93 ir_op *op_ia32_PrefetchNTA = NULL;
94 ir_op *op_ia32_PrefetchT0 = NULL;
95 ir_op *op_ia32_PrefetchT1 = NULL;
96 ir_op *op_ia32_PrefetchT2 = NULL;
97 ir_op *op_ia32_PrefetchW = NULL;
98 ir_op *op_ia32_Pslld = NULL;
99 ir_op *op_ia32_Psllq = NULL;
100 ir_op *op_ia32_Psrld = NULL;
101 ir_op *op_ia32_Push = NULL;
102 ir_op *op_ia32_PushEax = NULL;
103 ir_op *op_ia32_Return = NULL;
104 ir_op *op_ia32_Rol = NULL;
105 ir_op *op_ia32_RolMem = NULL;
106 ir_op *op_ia32_Ror = NULL;
107 ir_op *op_ia32_RorMem = NULL;
108 ir_op *op_ia32_Sahf = NULL;
109 ir_op *op_ia32_Sar = NULL;
110 ir_op *op_ia32_SarMem = NULL;
111 ir_op *op_ia32_Sbb = NULL;
112 ir_op *op_ia32_Sbb0 = NULL;
113 ir_op *op_ia32_Setcc = NULL;
114 ir_op *op_ia32_SetccMem = NULL;
115 ir_op *op_ia32_Shl = NULL;
116 ir_op *op_ia32_ShlD = NULL;
117 ir_op *op_ia32_ShlMem = NULL;
118 ir_op *op_ia32_Shr = NULL;
119 ir_op *op_ia32_ShrD = NULL;
120 ir_op *op_ia32_ShrMem = NULL;
121 ir_op *op_ia32_Stc = NULL;
122 ir_op *op_ia32_Store = NULL;
123 ir_op *op_ia32_Sub = NULL;
124 ir_op *op_ia32_SubMem = NULL;
125 ir_op *op_ia32_SubSP = NULL;
126 ir_op *op_ia32_Subs = NULL;
127 ir_op *op_ia32_SwitchJmp = NULL;
128 ir_op *op_ia32_Test = NULL;
129 ir_op *op_ia32_UD2 = NULL;
130 ir_op *op_ia32_Ucomis = NULL;
131 ir_op *op_ia32_Xor = NULL;
132 ir_op *op_ia32_Xor0 = NULL;
133 ir_op *op_ia32_XorHighLow = NULL;
134 ir_op *op_ia32_XorMem = NULL;
135 ir_op *op_ia32_Xorp = NULL;
136 ir_op *op_ia32_emms = NULL;
137 ir_op *op_ia32_fabs = NULL;
138 ir_op *op_ia32_fadd = NULL;
139 ir_op *op_ia32_fchs = NULL;
140 ir_op *op_ia32_fdiv = NULL;
141 ir_op *op_ia32_fdup = NULL;
142 ir_op *op_ia32_femms = NULL;
143 ir_op *op_ia32_ffreep = NULL;
144 ir_op *op_ia32_fild = NULL;
145 ir_op *op_ia32_fist = NULL;
146 ir_op *op_ia32_fistp = NULL;
147 ir_op *op_ia32_fisttp = NULL;
148 ir_op *op_ia32_fld = NULL;
149 ir_op *op_ia32_fld1 = NULL;
150 ir_op *op_ia32_fldl2e = NULL;
151 ir_op *op_ia32_fldl2t = NULL;
152 ir_op *op_ia32_fldlg2 = NULL;
153 ir_op *op_ia32_fldln2 = NULL;
154 ir_op *op_ia32_fldpi = NULL;
155 ir_op *op_ia32_fldz = NULL;
156 ir_op *op_ia32_fmul = NULL;
157 ir_op *op_ia32_fpop = NULL;
158 ir_op *op_ia32_fst = NULL;
159 ir_op *op_ia32_fstp = NULL;
160 ir_op *op_ia32_fsub = NULL;
161 ir_op *op_ia32_fxch = NULL;
162 ir_op *op_ia32_l_Adc = NULL;
163 ir_op *op_ia32_l_Add = NULL;
164 ir_op *op_ia32_l_FloattoLL = NULL;
165 ir_op *op_ia32_l_IMul = NULL;
166 ir_op *op_ia32_l_LLtoFloat = NULL;
167 ir_op *op_ia32_l_Minus64 = NULL;
168 ir_op *op_ia32_l_Mul = NULL;
169 ir_op *op_ia32_l_Sbb = NULL;
170 ir_op *op_ia32_l_Sub = NULL;
171 ir_op *op_ia32_xAllOnes = NULL;
172 ir_op *op_ia32_xLoad = NULL;
173 ir_op *op_ia32_xPzero = NULL;
174 ir_op *op_ia32_xStore = NULL;
175 ir_op *op_ia32_xZero = NULL;
176 ir_op *op_ia32_xxLoad = NULL;
177 ir_op *op_ia32_xxStore = NULL;
178 
179 
180 static int ia32_opcode_start = -1;
181 
183 #define ia32_op_tag FOURCC('i', 'a', '3', '2')
184 
186 int is_ia32_op(const ir_op *op)
187 {
188  return get_op_tag(op) == ia32_op_tag;
189 }
190 
192 int is_ia32_irn(const ir_node *node)
193 {
194  return is_ia32_op(get_irn_op(node));
195 }
196 
197 int get_ia32_irn_opcode(const ir_node *node)
198 {
199  assert(is_ia32_irn(node));
200  return get_irn_opcode(node) - ia32_opcode_start;
201 }
202 
203 #undef BIT
204 #define BIT(x) (1 << (x))
205 
206 static const unsigned ia32_limit_gp_eax_ebx_ecx_edx[] = { BIT(REG_GP_EAX) | BIT(REG_GP_EBX) | BIT(REG_GP_ECX) | BIT(REG_GP_EDX), 0 };
207 static const unsigned ia32_limit_gp_esp[] = { BIT(REG_GP_ESP), 0 };
208 static const unsigned ia32_limit_gp_gp_NOREG[] = { BIT(REG_GP_GP_NOREG), 0 };
209 static const unsigned ia32_limit_gp_ebp[] = { BIT(REG_GP_EBP), 0 };
210 static const unsigned ia32_limit_fp_fp_NOREG[] = { BIT(REG_FP_FP_NOREG), 0 };
211 static const unsigned ia32_limit_xmm_xmm_NOREG[] = { BIT(REG_XMM_XMM_NOREG), 0 };
212 
213 static const arch_register_req_t ia32_requirements_gp_in_r3_in_r4 = {
214  .cls = &ia32_reg_classes[CLASS_ia32_gp],
215  .limited = NULL,
216  .should_be_same = 24,
217  .must_be_different = 0,
218  .width = 1,
219 };
220 
221 static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx = {
222  .cls = &ia32_reg_classes[CLASS_ia32_gp],
223  .limited = ia32_limit_gp_eax_ebx_ecx_edx,
224  .should_be_same = 0,
225  .must_be_different = 0,
226  .width = 1,
227 };
228 
229 static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4 = {
230  .cls = &ia32_reg_classes[CLASS_ia32_gp],
231  .limited = ia32_limit_gp_eax_ebx_ecx_edx,
232  .should_be_same = 24,
233  .must_be_different = 0,
234  .width = 1,
235 };
236 
237 static const arch_register_req_t ia32_requirements_gp_esp_I = {
238  .cls = &ia32_reg_classes[CLASS_ia32_gp],
239  .limited = ia32_limit_gp_esp,
240  .should_be_same = 0,
241  .must_be_different = 0,
242  .width = 1,
243  .ignore = true,
244 };
245 
246 static const arch_register_req_t ia32_requirements_xmm_in_r3_in_r4 = {
247  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
248  .limited = NULL,
249  .should_be_same = 24,
250  .must_be_different = 0,
251  .width = 1,
252 };
253 
254 static const arch_register_req_t ia32_requirements_xmm_in_r3_not_in_r4 = {
255  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
256  .limited = NULL,
257  .should_be_same = 8,
258  .must_be_different = 16,
259  .width = 1,
260 };
261 
262 static const arch_register_req_t ia32_requirements_gp_in_r0 = {
263  .cls = &ia32_reg_classes[CLASS_ia32_gp],
264  .limited = NULL,
265  .should_be_same = 1,
266  .must_be_different = 0,
267  .width = 1,
268 };
269 
270 static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx_in_r0 = {
271  .cls = &ia32_reg_classes[CLASS_ia32_gp],
272  .limited = ia32_limit_gp_eax_ebx_ecx_edx,
273  .should_be_same = 1,
274  .must_be_different = 0,
275  .width = 1,
276 };
277 
278 static const arch_register_req_t ia32_requirements_gp_gp_NOREG_I = {
279  .cls = &ia32_reg_classes[CLASS_ia32_gp],
280  .limited = ia32_limit_gp_gp_NOREG,
281  .should_be_same = 0,
282  .must_be_different = 0,
283  .width = 1,
284  .ignore = true,
285 };
286 
287 static const arch_register_req_t ia32_requirements_gp_ebp_I = {
288  .cls = &ia32_reg_classes[CLASS_ia32_gp],
289  .limited = ia32_limit_gp_ebp,
290  .should_be_same = 0,
291  .must_be_different = 0,
292  .width = 1,
293  .ignore = true,
294 };
295 
296 static const arch_register_req_t ia32_requirements_gp_in_r1 = {
297  .cls = &ia32_reg_classes[CLASS_ia32_gp],
298  .limited = NULL,
299  .should_be_same = 2,
300  .must_be_different = 0,
301  .width = 1,
302 };
303 
304 static const arch_register_req_t ia32_requirements_fp_fp_NOREG_I = {
305  .cls = &ia32_reg_classes[CLASS_ia32_fp],
306  .limited = ia32_limit_fp_fp_NOREG,
307  .should_be_same = 0,
308  .must_be_different = 0,
309  .width = 1,
310  .ignore = true,
311 };
312 
313 static const arch_register_req_t ia32_requirements_xmm_xmm_NOREG_I = {
314  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
315  .limited = ia32_limit_xmm_xmm_NOREG,
316  .should_be_same = 0,
317  .must_be_different = 0,
318  .width = 1,
319  .ignore = true,
320 };
321 
322 static const arch_register_req_t ia32_requirements_xmm_in_r0_not_in_r1 = {
323  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
324  .limited = NULL,
325  .should_be_same = 1,
326  .must_be_different = 2,
327  .width = 1,
328 };
329 
330 static const arch_register_req_t ia32_requirements_gp_in_r0_not_in_r1 = {
331  .cls = &ia32_reg_classes[CLASS_ia32_gp],
332  .limited = NULL,
333  .should_be_same = 1,
334  .must_be_different = 2,
335  .width = 1,
336 };
337 
338 static const arch_register_req_t ia32_requirements_gp_in_r3 = {
339  .cls = &ia32_reg_classes[CLASS_ia32_gp],
340  .limited = NULL,
341  .should_be_same = 8,
342  .must_be_different = 0,
343  .width = 1,
344 };
345 
346 static const arch_register_req_t ia32_requirements_gp_in_r0_not_in_r1_not_in_r2 = {
347  .cls = &ia32_reg_classes[CLASS_ia32_gp],
348  .limited = NULL,
349  .should_be_same = 1,
350  .must_be_different = 6,
351  .width = 1,
352 };
353 
354 static const arch_register_req_t ia32_requirements_gp_in_r0_in_r1 = {
355  .cls = &ia32_reg_classes[CLASS_ia32_gp],
356  .limited = NULL,
357  .should_be_same = 3,
358  .must_be_different = 0,
359  .width = 1,
360 };
361 
362 static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx_in_r3 = {
363  .cls = &ia32_reg_classes[CLASS_ia32_gp],
364  .limited = ia32_limit_gp_eax_ebx_ecx_edx,
365  .should_be_same = 8,
366  .must_be_different = 0,
367  .width = 1,
368 };
369 
370 static const arch_register_req_t ia32_requirements_xmm_in_r3 = {
371  .cls = &ia32_reg_classes[CLASS_ia32_xmm],
372  .limited = NULL,
373  .should_be_same = 8,
374  .must_be_different = 0,
375  .width = 1,
376 };
377 
378 static const arch_register_req_t ia32_requirements_fp_fp_K = {
379  .cls = &ia32_reg_classes[CLASS_ia32_fp],
380  .width = 1,
381  .kills_value = true,
382 };
383 
384 
385 
386 ir_node *new_bd_ia32_Adc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *eflags, x86_insn_size_t size)
387 {
388  static arch_register_req_t const *in_reqs[] = {
389  &ia32_class_reg_req_gp,
390  &ia32_class_reg_req_gp,
391  &arch_memory_requirement,
392  &ia32_class_reg_req_gp,
393  &ia32_class_reg_req_gp,
394  &ia32_class_reg_req_flags,
395  };
396 
397  /* construct in array */
398  ir_node *const in[] = {
399  base,
400  index,
401  mem,
402  left,
403  right,
404  eflags,
405  };
406 
407  ir_graph *const irg = get_irn_irg(block);
408  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Adc, ia32_mode_gp, 6, in);
409 
410  /* flags */
411  arch_irn_flags_t irn_flags = arch_irn_flags_none;
412  irn_flags |= arch_irn_flag_modify_flags;
413 
414  /* init node attributes */
415  int const n_res = 3;
416  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
417  (void)attr; /* avoid potential warning */
418  x86_condition_code_t condition_code = x86_cc_carry;
419  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
420  init_ia32_condcode_attributes(res, condition_code);
421  set_ia32_am_support(res, ia32_am_binary);
422  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
423  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
424  out_infos[1].req = &ia32_class_reg_req_flags;
425  out_infos[2].req = &arch_memory_requirement;
426 
427  verify_new_node(res);
428  return optimize_node(res);
429 }
430 
431 ir_node *new_bd_ia32_Add(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
432 {
433  static arch_register_req_t const *in_reqs[] = {
434  &ia32_class_reg_req_gp,
435  &ia32_class_reg_req_gp,
436  &arch_memory_requirement,
437  &ia32_class_reg_req_gp,
438  &ia32_class_reg_req_gp,
439  };
440 
441  /* construct in array */
442  ir_node *const in[] = {
443  base,
444  index,
445  mem,
446  left,
447  right,
448  };
449 
450  ir_graph *const irg = get_irn_irg(block);
451  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Add, ia32_mode_gp, 5, in);
452 
453  /* flags */
454  arch_irn_flags_t irn_flags = arch_irn_flags_none;
455  irn_flags |= arch_irn_flag_modify_flags;
456  irn_flags |= arch_irn_flag_rematerializable;
457 
458  /* init node attributes */
459  int const n_res = 3;
460  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
461  (void)attr; /* avoid potential warning */
462  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
463  set_ia32_am_support(res, ia32_am_binary);
464  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
465  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
466  out_infos[1].req = &ia32_class_reg_req_flags;
467  out_infos[2].req = &arch_memory_requirement;
468 
469  verify_new_node(res);
470  return optimize_node(res);
471 }
472 
473 ir_node *new_bd_ia32_Add_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
474 {
475  static arch_register_req_t const *in_reqs[] = {
476  &ia32_class_reg_req_gp,
477  &ia32_class_reg_req_gp,
478  &arch_memory_requirement,
479  &ia32_requirements_gp_eax_ebx_ecx_edx,
480  &ia32_requirements_gp_eax_ebx_ecx_edx,
481  };
482 
483  /* construct in array */
484  ir_node *const in[] = {
485  base,
486  index,
487  mem,
488  left,
489  right,
490  };
491 
492  ir_graph *const irg = get_irn_irg(block);
493  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Add, ia32_mode_gp, 5, in);
494 
495  /* flags */
496  arch_irn_flags_t irn_flags = arch_irn_flags_none;
497  irn_flags |= arch_irn_flag_modify_flags;
498  irn_flags |= arch_irn_flag_rematerializable;
499 
500  /* init node attributes */
501  int const n_res = 3;
502  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
503  (void)attr; /* avoid potential warning */
504  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
505  set_ia32_am_support(res, ia32_am_binary);
506  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
507  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
508  out_infos[1].req = &ia32_class_reg_req_flags;
509  out_infos[2].req = &arch_memory_requirement;
510 
511  verify_new_node(res);
512  return optimize_node(res);
513 }
514 
515 ir_node *new_bd_ia32_AddMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
516 {
517  static arch_register_req_t const *in_reqs[] = {
518  &ia32_class_reg_req_gp,
519  &ia32_class_reg_req_gp,
520  &arch_memory_requirement,
521  &ia32_class_reg_req_gp,
522  };
523 
524  /* construct in array */
525  ir_node *const in[] = {
526  base,
527  index,
528  mem,
529  val,
530  };
531 
532  ir_graph *const irg = get_irn_irg(block);
533  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AddMem, mode_T, 4, in);
534 
535  /* flags */
536  arch_irn_flags_t irn_flags = arch_irn_flags_none;
537  irn_flags |= arch_irn_flag_modify_flags;
538  irn_flags |= arch_irn_flag_rematerializable;
539 
540  /* init node attributes */
541  int const n_res = 3;
542  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
543  (void)attr; /* avoid potential warning */
544  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
545  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
546  out_infos[0].req = &arch_no_requirement;
547  out_infos[1].req = &ia32_class_reg_req_flags;
548  out_infos[2].req = &arch_memory_requirement;
549 
550  verify_new_node(res);
551  return optimize_node(res);
552 }
553 
554 ir_node *new_bd_ia32_AddMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
555 {
556  static arch_register_req_t const *in_reqs[] = {
557  &ia32_class_reg_req_gp,
558  &ia32_class_reg_req_gp,
559  &arch_memory_requirement,
560  &ia32_requirements_gp_eax_ebx_ecx_edx,
561  };
562 
563  /* construct in array */
564  ir_node *const in[] = {
565  base,
566  index,
567  mem,
568  val,
569  };
570 
571  ir_graph *const irg = get_irn_irg(block);
572  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AddMem, mode_T, 4, in);
573 
574  /* flags */
575  arch_irn_flags_t irn_flags = arch_irn_flags_none;
576  irn_flags |= arch_irn_flag_modify_flags;
577  irn_flags |= arch_irn_flag_rematerializable;
578 
579  /* init node attributes */
580  int const n_res = 3;
581  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
582  (void)attr; /* avoid potential warning */
583  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
584  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
585  out_infos[0].req = &arch_no_requirement;
586  out_infos[1].req = &ia32_class_reg_req_flags;
587  out_infos[2].req = &arch_memory_requirement;
588 
589  verify_new_node(res);
590  return optimize_node(res);
591 }
592 
593 ir_node *new_bd_ia32_AddSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *amount)
594 {
595  static arch_register_req_t const *in_reqs[] = {
596  &ia32_class_reg_req_gp,
597  &ia32_class_reg_req_gp,
598  &arch_memory_requirement,
599  &ia32_single_reg_req_gp_esp,
600  &ia32_class_reg_req_gp,
601  };
602 
603  /* construct in array */
604  ir_node *const in[] = {
605  base,
606  index,
607  mem,
608  stack,
609  amount,
610  };
611 
612  ir_graph *const irg = get_irn_irg(block);
613  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AddSP, mode_T, 5, in);
614 
615  /* flags */
616  arch_irn_flags_t irn_flags = arch_irn_flags_none;
617  irn_flags |= arch_irn_flag_modify_flags;
618 
619  /* init node attributes */
620  int const n_res = 2;
621  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
622  (void)attr; /* avoid potential warning */
623  x86_insn_size_t const size = X86_SIZE_32;
624  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
625  set_ia32_am_support(res, ia32_am_binary);
626  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
627  out_infos[0].req = &ia32_requirements_gp_esp_I;
628  out_infos[1].req = &arch_memory_requirement;
629 
630  verify_new_node(res);
631  return optimize_node(res);
632 }
633 
634 ir_node *new_bd_ia32_Adds(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
635 {
636  static arch_register_req_t const *in_reqs[] = {
637  &ia32_class_reg_req_gp,
638  &ia32_class_reg_req_gp,
639  &arch_memory_requirement,
640  &ia32_class_reg_req_xmm,
641  &ia32_class_reg_req_xmm,
642  };
643 
644  /* construct in array */
645  ir_node *const in[] = {
646  base,
647  index,
648  mem,
649  left,
650  right,
651  };
652 
653  ir_graph *const irg = get_irn_irg(block);
654  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Adds, ia32_mode_float64, 5, in);
655 
656  /* flags */
657  arch_irn_flags_t irn_flags = arch_irn_flags_none;
658  irn_flags |= arch_irn_flag_rematerializable;
659 
660  /* init node attributes */
661  int const n_res = 3;
662  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
663  (void)attr; /* avoid potential warning */
664  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
665  set_ia32_am_support(res, ia32_am_binary);
666  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
667  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
668  out_infos[1].req = &ia32_class_reg_req_flags;
669  out_infos[2].req = &arch_memory_requirement;
670 
671  verify_new_node(res);
672  return optimize_node(res);
673 }
674 
675 ir_node *new_bd_ia32_And(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
676 {
677  static arch_register_req_t const *in_reqs[] = {
678  &ia32_class_reg_req_gp,
679  &ia32_class_reg_req_gp,
680  &arch_memory_requirement,
681  &ia32_class_reg_req_gp,
682  &ia32_class_reg_req_gp,
683  };
684 
685  /* construct in array */
686  ir_node *const in[] = {
687  base,
688  index,
689  mem,
690  left,
691  right,
692  };
693 
694  ir_graph *const irg = get_irn_irg(block);
695  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_And, ia32_mode_gp, 5, in);
696 
697  /* flags */
698  arch_irn_flags_t irn_flags = arch_irn_flags_none;
699  irn_flags |= arch_irn_flag_modify_flags;
700  irn_flags |= arch_irn_flag_rematerializable;
701 
702  /* init node attributes */
703  int const n_res = 3;
704  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
705  (void)attr; /* avoid potential warning */
706  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
707  set_ia32_am_support(res, ia32_am_binary);
708  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
709  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
710  out_infos[1].req = &ia32_class_reg_req_flags;
711  out_infos[2].req = &arch_memory_requirement;
712 
713  verify_new_node(res);
714  return optimize_node(res);
715 }
716 
717 ir_node *new_bd_ia32_And_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
718 {
719  static arch_register_req_t const *in_reqs[] = {
720  &ia32_class_reg_req_gp,
721  &ia32_class_reg_req_gp,
722  &arch_memory_requirement,
723  &ia32_requirements_gp_eax_ebx_ecx_edx,
724  &ia32_requirements_gp_eax_ebx_ecx_edx,
725  };
726 
727  /* construct in array */
728  ir_node *const in[] = {
729  base,
730  index,
731  mem,
732  left,
733  right,
734  };
735 
736  ir_graph *const irg = get_irn_irg(block);
737  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_And, ia32_mode_gp, 5, in);
738 
739  /* flags */
740  arch_irn_flags_t irn_flags = arch_irn_flags_none;
741  irn_flags |= arch_irn_flag_modify_flags;
742  irn_flags |= arch_irn_flag_rematerializable;
743 
744  /* init node attributes */
745  int const n_res = 3;
746  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
747  (void)attr; /* avoid potential warning */
748  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
749  set_ia32_am_support(res, ia32_am_binary);
750  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
751  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
752  out_infos[1].req = &ia32_class_reg_req_flags;
753  out_infos[2].req = &arch_memory_requirement;
754 
755  verify_new_node(res);
756  return optimize_node(res);
757 }
758 
759 ir_node *new_bd_ia32_AndMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
760 {
761  static arch_register_req_t const *in_reqs[] = {
762  &ia32_class_reg_req_gp,
763  &ia32_class_reg_req_gp,
764  &arch_memory_requirement,
765  &ia32_class_reg_req_gp,
766  };
767 
768  /* construct in array */
769  ir_node *const in[] = {
770  base,
771  index,
772  mem,
773  val,
774  };
775 
776  ir_graph *const irg = get_irn_irg(block);
777  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AndMem, mode_T, 4, in);
778 
779  /* flags */
780  arch_irn_flags_t irn_flags = arch_irn_flags_none;
781  irn_flags |= arch_irn_flag_modify_flags;
782  irn_flags |= arch_irn_flag_rematerializable;
783 
784  /* init node attributes */
785  int const n_res = 3;
786  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
787  (void)attr; /* avoid potential warning */
788  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
789  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
790  out_infos[0].req = &arch_no_requirement;
791  out_infos[1].req = &ia32_class_reg_req_flags;
792  out_infos[2].req = &arch_memory_requirement;
793 
794  verify_new_node(res);
795  return optimize_node(res);
796 }
797 
798 ir_node *new_bd_ia32_AndMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
799 {
800  static arch_register_req_t const *in_reqs[] = {
801  &ia32_class_reg_req_gp,
802  &ia32_class_reg_req_gp,
803  &arch_memory_requirement,
804  &ia32_requirements_gp_eax_ebx_ecx_edx,
805  };
806 
807  /* construct in array */
808  ir_node *const in[] = {
809  base,
810  index,
811  mem,
812  val,
813  };
814 
815  ir_graph *const irg = get_irn_irg(block);
816  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_AndMem, mode_T, 4, in);
817 
818  /* flags */
819  arch_irn_flags_t irn_flags = arch_irn_flags_none;
820  irn_flags |= arch_irn_flag_modify_flags;
821  irn_flags |= arch_irn_flag_rematerializable;
822 
823  /* init node attributes */
824  int const n_res = 3;
825  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
826  (void)attr; /* avoid potential warning */
827  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
828  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
829  out_infos[0].req = &arch_no_requirement;
830  out_infos[1].req = &ia32_class_reg_req_flags;
831  out_infos[2].req = &arch_memory_requirement;
832 
833  verify_new_node(res);
834  return optimize_node(res);
835 }
836 
837 ir_node *new_bd_ia32_Andnp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
838 {
839  static arch_register_req_t const *in_reqs[] = {
840  &ia32_class_reg_req_gp,
841  &ia32_class_reg_req_gp,
842  &arch_memory_requirement,
843  &ia32_class_reg_req_xmm,
844  &ia32_class_reg_req_xmm,
845  };
846 
847  /* construct in array */
848  ir_node *const in[] = {
849  base,
850  index,
851  mem,
852  left,
853  right,
854  };
855 
856  ir_graph *const irg = get_irn_irg(block);
857  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Andnp, ia32_mode_float64, 5, in);
858 
859  /* flags */
860  arch_irn_flags_t irn_flags = arch_irn_flags_none;
861  irn_flags |= arch_irn_flag_rematerializable;
862 
863  /* init node attributes */
864  int const n_res = 3;
865  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
866  (void)attr; /* avoid potential warning */
867  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
868  set_ia32_am_support(res, ia32_am_binary);
869  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
870  out_infos[0].req = &ia32_requirements_xmm_in_r3_not_in_r4;
871  out_infos[1].req = &ia32_class_reg_req_flags;
872  out_infos[2].req = &arch_memory_requirement;
873 
874  verify_new_node(res);
875  return optimize_node(res);
876 }
877 
878 ir_node *new_bd_ia32_Andp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
879 {
880  static arch_register_req_t const *in_reqs[] = {
881  &ia32_class_reg_req_gp,
882  &ia32_class_reg_req_gp,
883  &arch_memory_requirement,
884  &ia32_class_reg_req_xmm,
885  &ia32_class_reg_req_xmm,
886  };
887 
888  /* construct in array */
889  ir_node *const in[] = {
890  base,
891  index,
892  mem,
893  left,
894  right,
895  };
896 
897  ir_graph *const irg = get_irn_irg(block);
898  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Andp, ia32_mode_float64, 5, in);
899 
900  /* flags */
901  arch_irn_flags_t irn_flags = arch_irn_flags_none;
902  irn_flags |= arch_irn_flag_rematerializable;
903 
904  /* init node attributes */
905  int const n_res = 3;
906  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
907  (void)attr; /* avoid potential warning */
908  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
909  set_ia32_am_support(res, ia32_am_binary);
910  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
911  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
912  out_infos[1].req = &ia32_class_reg_req_flags;
913  out_infos[2].req = &arch_memory_requirement;
914 
915  verify_new_node(res);
916  return optimize_node(res);
917 }
918 
919 ir_node *new_bd_ia32_Breakpoint(dbg_info *dbgi, ir_node *block, ir_node *mem)
920 {
921  static arch_register_req_t const *in_reqs[] = {
922  &arch_memory_requirement,
923  };
924 
925  /* construct in array */
926  ir_node *const in[] = {
927  mem,
928  };
929 
930  ir_graph *const irg = get_irn_irg(block);
931  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Breakpoint, mode_M, 1, in);
932 
933  /* flags */
934  arch_irn_flags_t irn_flags = arch_irn_flags_none;
935 
936  /* init node attributes */
937  int const n_res = 1;
938  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
939  (void)attr; /* avoid potential warning */
940  x86_insn_size_t const size = X86_SIZE_32;
941  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
942  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
943  out_infos[0].req = &arch_memory_requirement;
944 
945  verify_new_node(res);
946  return optimize_node(res);
947 }
948 
949 ir_node *new_bd_ia32_Bsf(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size)
950 {
951  static arch_register_req_t const *in_reqs[] = {
952  &ia32_class_reg_req_gp,
953  &ia32_class_reg_req_gp,
954  &arch_memory_requirement,
955  &ia32_class_reg_req_gp,
956  };
957 
958  /* construct in array */
959  ir_node *const in[] = {
960  base,
961  index,
962  mem,
963  operand,
964  };
965 
966  ir_graph *const irg = get_irn_irg(block);
967  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bsf, ia32_mode_gp, 4, in);
968 
969  /* flags */
970  arch_irn_flags_t irn_flags = arch_irn_flags_none;
971  irn_flags |= arch_irn_flag_modify_flags;
972  irn_flags |= arch_irn_flag_rematerializable;
973 
974  /* init node attributes */
975  int const n_res = 3;
976  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
977  (void)attr; /* avoid potential warning */
978  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
979  set_ia32_am_support(res, ia32_am_unary);
980  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
981  out_infos[0].req = &ia32_class_reg_req_gp;
982  out_infos[1].req = &ia32_class_reg_req_flags;
983  out_infos[2].req = &arch_memory_requirement;
984 
985  verify_new_node(res);
986  return optimize_node(res);
987 }
988 
989 ir_node *new_bd_ia32_Bsr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size)
990 {
991  static arch_register_req_t const *in_reqs[] = {
992  &ia32_class_reg_req_gp,
993  &ia32_class_reg_req_gp,
994  &arch_memory_requirement,
995  &ia32_class_reg_req_gp,
996  };
997 
998  /* construct in array */
999  ir_node *const in[] = {
1000  base,
1001  index,
1002  mem,
1003  operand,
1004  };
1005 
1006  ir_graph *const irg = get_irn_irg(block);
1007  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bsr, ia32_mode_gp, 4, in);
1008 
1009  /* flags */
1010  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1011  irn_flags |= arch_irn_flag_modify_flags;
1012  irn_flags |= arch_irn_flag_rematerializable;
1013 
1014  /* init node attributes */
1015  int const n_res = 3;
1016  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1017  (void)attr; /* avoid potential warning */
1018  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1019  set_ia32_am_support(res, ia32_am_unary);
1020  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1021  out_infos[0].req = &ia32_class_reg_req_gp;
1022  out_infos[1].req = &ia32_class_reg_req_flags;
1023  out_infos[2].req = &arch_memory_requirement;
1024 
1025  verify_new_node(res);
1026  return optimize_node(res);
1027 }
1028 
1029 ir_node *new_bd_ia32_Bswap(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
1030 {
1031  static arch_register_req_t const *in_reqs[] = {
1032  &ia32_class_reg_req_gp,
1033  };
1034 
1035  /* construct in array */
1036  ir_node *const in[] = {
1037  val,
1038  };
1039 
1040  ir_graph *const irg = get_irn_irg(block);
1041  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bswap, ia32_mode_gp, 1, in);
1042 
1043  /* flags */
1044  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1045  irn_flags |= arch_irn_flag_rematerializable;
1046 
1047  /* init node attributes */
1048  int const n_res = 1;
1049  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1050  (void)attr; /* avoid potential warning */
1051  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1052  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1053  out_infos[0].req = &ia32_requirements_gp_in_r0;
1054 
1055  verify_new_node(res);
1056  return optimize_node(res);
1057 }
1058 
1059 ir_node *new_bd_ia32_Bswap16(dbg_info *dbgi, ir_node *block, ir_node *val)
1060 {
1061  static arch_register_req_t const *in_reqs[] = {
1062  &ia32_requirements_gp_eax_ebx_ecx_edx,
1063  };
1064 
1065  /* construct in array */
1066  ir_node *const in[] = {
1067  val,
1068  };
1069 
1070  ir_graph *const irg = get_irn_irg(block);
1071  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bswap16, ia32_mode_gp, 1, in);
1072 
1073  /* flags */
1074  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1075  irn_flags |= arch_irn_flag_rematerializable;
1076 
1077  /* init node attributes */
1078  int const n_res = 1;
1079  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1080  (void)attr; /* avoid potential warning */
1081  x86_insn_size_t const size = X86_SIZE_8;
1082  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1083  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1084  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r0;
1085 
1086  verify_new_node(res);
1087  return optimize_node(res);
1088 }
1089 
1090 ir_node *new_bd_ia32_Bt(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, x86_insn_size_t size)
1091 {
1092  static arch_register_req_t const *in_reqs[] = {
1093  &ia32_class_reg_req_gp,
1094  &ia32_class_reg_req_gp,
1095  };
1096 
1097  /* construct in array */
1098  ir_node *const in[] = {
1099  left,
1100  right,
1101  };
1102 
1103  ir_graph *const irg = get_irn_irg(block);
1104  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Bt, ia32_mode_flags, 2, in);
1105 
1106  /* flags */
1107  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1108  irn_flags |= arch_irn_flag_modify_flags;
1109  irn_flags |= arch_irn_flag_rematerializable;
1110 
1111  /* init node attributes */
1112  int const n_res = 1;
1113  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1114  (void)attr; /* avoid potential warning */
1115  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1116  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1117  out_infos[0].req = &ia32_class_reg_req_flags;
1118 
1119  verify_new_node(res);
1120  return optimize_node(res);
1121 }
1122 
1123 ir_node *new_bd_ia32_CMovcc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val_false, ir_node *val_true, ir_node *eflags, x86_insn_size_t size, x86_condition_code_t condition_code)
1124 {
1125  static arch_register_req_t const *in_reqs[] = {
1126  &ia32_class_reg_req_gp,
1127  &ia32_class_reg_req_gp,
1128  &arch_memory_requirement,
1129  &ia32_class_reg_req_gp,
1130  &ia32_class_reg_req_gp,
1131  &ia32_single_reg_req_flags_eflags,
1132  };
1133 
1134  /* construct in array */
1135  ir_node *const in[] = {
1136  base,
1137  index,
1138  mem,
1139  val_false,
1140  val_true,
1141  eflags,
1142  };
1143 
1144  ir_graph *const irg = get_irn_irg(block);
1145  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CMovcc, ia32_mode_gp, 6, in);
1146 
1147  /* flags */
1148  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1149 
1150  /* init node attributes */
1151  int const n_res = 3;
1152  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
1153  (void)attr; /* avoid potential warning */
1154  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1155  init_ia32_condcode_attributes(res, condition_code);
1156  set_ia32_am_support(res, ia32_am_binary);
1157  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1158  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
1159  out_infos[1].req = &arch_no_requirement;
1160  out_infos[2].req = &arch_memory_requirement;
1161 
1162  verify_new_node(res);
1163  return optimize_node(res);
1164 }
1165 
1166 ir_node *new_bd_ia32_Call(dbg_info *dbgi, ir_node *block, int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs, int n_res, uint8_t pop, uint8_t n_reg_results)
1167 {
1168 
1169 
1170  ir_graph *const irg = get_irn_irg(block);
1171  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Call, mode_T, arity, in);
1172 
1173  /* flags */
1174  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1175  irn_flags |= arch_irn_flag_modify_flags;
1176 
1177  /* init node attributes */
1178  ia32_call_attr_t *const attr = (ia32_call_attr_t*)get_irn_generic_attr(res);
1179  (void)attr; /* avoid potential warning */
1180  x86_insn_size_t const size = X86_SIZE_32;
1181  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1182  init_ia32_call_attributes(res, pop, n_reg_results);
1183  set_ia32_am_support(res, ia32_am_unary);
1184 
1185  verify_new_node(res);
1186  return optimize_node(res);
1187 }
1188 
1189 ir_node *new_bd_ia32_ChangeCW(dbg_info *dbgi, ir_node *block)
1190 {
1191  arch_register_req_t const **const in_reqs = NULL;
1192 
1193 
1194  ir_graph *const irg = get_irn_irg(block);
1195  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ChangeCW, ia32_mode_fpcw, 0, NULL);
1196 
1197  /* flags */
1198  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1199  irn_flags |= arch_irn_flag_not_scheduled;
1200 
1201  /* init node attributes */
1202  int const n_res = 1;
1203  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1204  (void)attr; /* avoid potential warning */
1205  x86_insn_size_t const size = X86_SIZE_32;
1206  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1207  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1208  out_infos[0].req = &ia32_single_reg_req_fp_cw_fpcw;
1209 
1210  verify_new_node(res);
1211  return optimize_node(res);
1212 }
1213 
1214 ir_node *new_bd_ia32_Cltd(dbg_info *dbgi, ir_node *block, ir_node *val)
1215 {
1216  static arch_register_req_t const *in_reqs[] = {
1217  &ia32_single_reg_req_gp_eax,
1218  };
1219 
1220  /* construct in array */
1221  ir_node *const in[] = {
1222  val,
1223  };
1224 
1225  ir_graph *const irg = get_irn_irg(block);
1226  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cltd, ia32_mode_gp, 1, in);
1227 
1228  /* flags */
1229  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1230 
1231  /* init node attributes */
1232  int const n_res = 1;
1233  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1234  (void)attr; /* avoid potential warning */
1235  x86_insn_size_t const size = X86_SIZE_32;
1236  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1237  arch_set_additional_pressure(res, &ia32_reg_classes[CLASS_ia32_gp], 1);
1238  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1239  out_infos[0].req = &ia32_single_reg_req_gp_edx;
1240 
1241  verify_new_node(res);
1242  return optimize_node(res);
1243 }
1244 
1245 ir_node *new_bd_ia32_Cmc(dbg_info *dbgi, ir_node *block, ir_node *op0)
1246 {
1247  static arch_register_req_t const *in_reqs[] = {
1248  &ia32_class_reg_req_flags,
1249  };
1250 
1251  /* construct in array */
1252  ir_node *const in[] = {
1253  op0,
1254  };
1255 
1256  ir_graph *const irg = get_irn_irg(block);
1257  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cmc, ia32_mode_flags, 1, in);
1258 
1259  /* flags */
1260  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1261  irn_flags |= arch_irn_flag_modify_flags;
1262 
1263  /* init node attributes */
1264  int const n_res = 1;
1265  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
1266  (void)attr; /* avoid potential warning */
1267  x86_condition_code_t condition_code = x86_cc_carry;
1268  x86_insn_size_t const size = X86_SIZE_32;
1269  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1270  init_ia32_condcode_attributes(res, condition_code);
1271  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1272  out_infos[0].req = &ia32_class_reg_req_flags;
1273 
1274  verify_new_node(res);
1275  return optimize_node(res);
1276 }
1277 
1278 ir_node *new_bd_ia32_Cmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted)
1279 {
1280  static arch_register_req_t const *in_reqs[] = {
1281  &ia32_class_reg_req_gp,
1282  &ia32_class_reg_req_gp,
1283  &arch_memory_requirement,
1284  &ia32_class_reg_req_gp,
1285  &ia32_class_reg_req_gp,
1286  };
1287 
1288  /* construct in array */
1289  ir_node *const in[] = {
1290  base,
1291  index,
1292  mem,
1293  left,
1294  right,
1295  };
1296 
1297  ir_graph *const irg = get_irn_irg(block);
1298  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cmp, ia32_mode_flags, 5, in);
1299 
1300  /* flags */
1301  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1302  irn_flags |= arch_irn_flag_modify_flags;
1303  irn_flags |= arch_irn_flag_rematerializable;
1304 
1305  /* init node attributes */
1306  int const n_res = 3;
1307  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1308  (void)attr; /* avoid potential warning */
1309  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1310  set_ia32_am_support(res, ia32_am_binary);
1311  attr->ins_permuted = ins_permuted;
1312  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1313  out_infos[0].req = &ia32_class_reg_req_flags;
1314  out_infos[1].req = &arch_no_requirement;
1315  out_infos[2].req = &arch_memory_requirement;
1316 
1317  verify_new_node(res);
1318  return optimize_node(res);
1319 }
1320 
1321 ir_node *new_bd_ia32_Cmp_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted)
1322 {
1323  static arch_register_req_t const *in_reqs[] = {
1324  &ia32_class_reg_req_gp,
1325  &ia32_class_reg_req_gp,
1326  &arch_memory_requirement,
1327  &ia32_requirements_gp_eax_ebx_ecx_edx,
1328  &ia32_requirements_gp_eax_ebx_ecx_edx,
1329  };
1330 
1331  /* construct in array */
1332  ir_node *const in[] = {
1333  base,
1334  index,
1335  mem,
1336  left,
1337  right,
1338  };
1339 
1340  ir_graph *const irg = get_irn_irg(block);
1341  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cmp, ia32_mode_flags, 5, in);
1342 
1343  /* flags */
1344  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1345  irn_flags |= arch_irn_flag_modify_flags;
1346  irn_flags |= arch_irn_flag_rematerializable;
1347 
1348  /* init node attributes */
1349  int const n_res = 3;
1350  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1351  (void)attr; /* avoid potential warning */
1352  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1353  set_ia32_am_support(res, ia32_am_binary);
1354  attr->ins_permuted = ins_permuted;
1355  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1356  out_infos[0].req = &ia32_class_reg_req_flags;
1357  out_infos[1].req = &arch_no_requirement;
1358  out_infos[2].req = &arch_memory_requirement;
1359 
1360  verify_new_node(res);
1361  return optimize_node(res);
1362 }
1363 
1364 ir_node *new_bd_ia32_CmpXChgMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *old, ir_node *new, x86_insn_size_t size)
1365 {
1366  static arch_register_req_t const *in_reqs[] = {
1367  &ia32_class_reg_req_gp,
1368  &ia32_class_reg_req_gp,
1369  &arch_memory_requirement,
1370  &ia32_single_reg_req_gp_eax,
1371  &ia32_class_reg_req_gp,
1372  };
1373 
1374  /* construct in array */
1375  ir_node *const in[] = {
1376  base,
1377  index,
1378  mem,
1379  old,
1380  new,
1381  };
1382 
1383  ir_graph *const irg = get_irn_irg(block);
1384  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CmpXChgMem, mode_T, 5, in);
1385 
1386  /* flags */
1387  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1388  irn_flags |= arch_irn_flag_modify_flags;
1389  irn_flags |= arch_irn_flag_rematerializable;
1390 
1391  /* init node attributes */
1392  int const n_res = 3;
1393  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1394  (void)attr; /* avoid potential warning */
1395  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1396  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1397  out_infos[0].req = &ia32_single_reg_req_gp_eax;
1398  out_infos[1].req = &ia32_class_reg_req_flags;
1399  out_infos[2].req = &arch_memory_requirement;
1400 
1401  verify_new_node(res);
1402  return optimize_node(res);
1403 }
1404 
1405 ir_node *new_bd_ia32_Const(dbg_info *dbgi, ir_node *block, const x86_imm32_t *imm)
1406 {
1407  arch_register_req_t const **const in_reqs = NULL;
1408 
1409 
1410  ir_graph *const irg = get_irn_irg(block);
1411  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Const, ia32_mode_gp, 0, NULL);
1412 
1413  /* flags */
1414  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1415  irn_flags |= arch_irn_flag_rematerializable;
1416 
1417  /* init node attributes */
1418  int const n_res = 1;
1419  ia32_immediate_attr_t *const attr = (ia32_immediate_attr_t*)get_irn_generic_attr(res);
1420  (void)attr; /* avoid potential warning */
1421  x86_insn_size_t const size = X86_SIZE_32;
1422  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1423  init_ia32_immediate_attributes(res, imm);
1424  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1425  out_infos[0].req = &ia32_class_reg_req_gp;
1426 
1427  verify_new_node(res);
1428  return optimize_node(res);
1429 }
1430 
1431 ir_node *new_bd_ia32_Conv_FP2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1432 {
1433  static arch_register_req_t const *in_reqs[] = {
1434  &ia32_class_reg_req_gp,
1435  &ia32_class_reg_req_gp,
1436  &arch_memory_requirement,
1437  &ia32_class_reg_req_xmm,
1438  };
1439 
1440  /* construct in array */
1441  ir_node *const in[] = {
1442  base,
1443  index,
1444  mem,
1445  val,
1446  };
1447 
1448  ir_graph *const irg = get_irn_irg(block);
1449  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_FP2FP, ia32_mode_float64, 4, in);
1450 
1451  /* flags */
1452  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1453 
1454  /* init node attributes */
1455  int const n_res = 2;
1456  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1457  (void)attr; /* avoid potential warning */
1458  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1459  set_ia32_am_support(res, ia32_am_unary);
1460  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1461  out_infos[0].req = &ia32_class_reg_req_xmm;
1462  out_infos[1].req = &arch_memory_requirement;
1463 
1464  verify_new_node(res);
1465  return optimize_node(res);
1466 }
1467 
1468 ir_node *new_bd_ia32_Conv_FP2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1469 {
1470  static arch_register_req_t const *in_reqs[] = {
1471  &ia32_class_reg_req_gp,
1472  &ia32_class_reg_req_gp,
1473  &arch_memory_requirement,
1474  &ia32_class_reg_req_xmm,
1475  };
1476 
1477  /* construct in array */
1478  ir_node *const in[] = {
1479  base,
1480  index,
1481  mem,
1482  val,
1483  };
1484 
1485  ir_graph *const irg = get_irn_irg(block);
1486  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_FP2I, ia32_mode_gp, 4, in);
1487 
1488  /* flags */
1489  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1490 
1491  /* init node attributes */
1492  int const n_res = 2;
1493  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1494  (void)attr; /* avoid potential warning */
1495  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1496  set_ia32_am_support(res, ia32_am_unary);
1497  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1498  out_infos[0].req = &ia32_class_reg_req_gp;
1499  out_infos[1].req = &arch_memory_requirement;
1500 
1501  verify_new_node(res);
1502  return optimize_node(res);
1503 }
1504 
1505 ir_node *new_bd_ia32_Conv_I2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1506 {
1507  static arch_register_req_t const *in_reqs[] = {
1508  &ia32_class_reg_req_gp,
1509  &ia32_class_reg_req_gp,
1510  &arch_memory_requirement,
1511  &ia32_class_reg_req_gp,
1512  };
1513 
1514  /* construct in array */
1515  ir_node *const in[] = {
1516  base,
1517  index,
1518  mem,
1519  val,
1520  };
1521 
1522  ir_graph *const irg = get_irn_irg(block);
1523  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_I2FP, ia32_mode_float64, 4, in);
1524 
1525  /* flags */
1526  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1527 
1528  /* init node attributes */
1529  int const n_res = 2;
1530  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1531  (void)attr; /* avoid potential warning */
1532  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1533  set_ia32_am_support(res, ia32_am_unary);
1534  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1535  out_infos[0].req = &ia32_class_reg_req_xmm;
1536  out_infos[1].req = &arch_memory_requirement;
1537 
1538  verify_new_node(res);
1539  return optimize_node(res);
1540 }
1541 
1542 ir_node *new_bd_ia32_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size, bool sign_extend)
1543 {
1544  static arch_register_req_t const *in_reqs[] = {
1545  &ia32_class_reg_req_gp,
1546  &ia32_class_reg_req_gp,
1547  &arch_memory_requirement,
1548  &ia32_class_reg_req_gp,
1549  };
1550 
1551  /* construct in array */
1552  ir_node *const in[] = {
1553  base,
1554  index,
1555  mem,
1556  val,
1557  };
1558 
1559  ir_graph *const irg = get_irn_irg(block);
1560  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_I2I, ia32_mode_gp, 4, in);
1561 
1562  /* flags */
1563  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1564 
1565  /* init node attributes */
1566  int const n_res = 5;
1567  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1568  (void)attr; /* avoid potential warning */
1569  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1570  set_ia32_am_support(res, ia32_am_unary);
1571  attr->sign_extend = sign_extend;
1572  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1573  out_infos[0].req = &ia32_class_reg_req_gp;
1574  out_infos[1].req = &arch_no_requirement;
1575  out_infos[2].req = &arch_memory_requirement;
1576  out_infos[3].req = &arch_exec_requirement;
1577  out_infos[4].req = &arch_exec_requirement;
1578 
1579  verify_new_node(res);
1580  return optimize_node(res);
1581 }
1582 
1583 ir_node *new_bd_ia32_Conv_I2I_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size, bool sign_extend)
1584 {
1585  static arch_register_req_t const *in_reqs[] = {
1586  &ia32_class_reg_req_gp,
1587  &ia32_class_reg_req_gp,
1588  &arch_memory_requirement,
1589  &ia32_requirements_gp_eax_ebx_ecx_edx,
1590  };
1591 
1592  /* construct in array */
1593  ir_node *const in[] = {
1594  base,
1595  index,
1596  mem,
1597  val,
1598  };
1599 
1600  ir_graph *const irg = get_irn_irg(block);
1601  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Conv_I2I, ia32_mode_gp, 4, in);
1602 
1603  /* flags */
1604  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1605 
1606  /* init node attributes */
1607  int const n_res = 5;
1608  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1609  (void)attr; /* avoid potential warning */
1610  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1611  set_ia32_am_support(res, ia32_am_unary);
1612  attr->sign_extend = sign_extend;
1613  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1614  out_infos[0].req = &ia32_class_reg_req_gp;
1615  out_infos[1].req = &arch_no_requirement;
1616  out_infos[2].req = &arch_memory_requirement;
1617  out_infos[3].req = &arch_exec_requirement;
1618  out_infos[4].req = &arch_exec_requirement;
1619 
1620  verify_new_node(res);
1621  return optimize_node(res);
1622 }
1623 
1624 ir_node *new_bd_ia32_CopyB(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *count, ir_node *mem, unsigned size)
1625 {
1626  static arch_register_req_t const *in_reqs[] = {
1627  &ia32_single_reg_req_gp_edi,
1628  &ia32_single_reg_req_gp_esi,
1629  &ia32_single_reg_req_gp_ecx,
1630  &arch_memory_requirement,
1631  };
1632 
1633  /* construct in array */
1634  ir_node *const in[] = {
1635  dest,
1636  source,
1637  count,
1638  mem,
1639  };
1640 
1641  ir_graph *const irg = get_irn_irg(block);
1642  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CopyB, mode_T, 4, in);
1643 
1644  /* flags */
1645  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1646 
1647  /* init node attributes */
1648  int const n_res = 4;
1649  ia32_copyb_attr_t *const attr = (ia32_copyb_attr_t*)get_irn_generic_attr(res);
1650  (void)attr; /* avoid potential warning */
1651  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1652  init_ia32_copyb_attributes(res, size);
1653  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1654  out_infos[0].req = &ia32_single_reg_req_gp_edi;
1655  out_infos[1].req = &ia32_single_reg_req_gp_esi;
1656  out_infos[2].req = &ia32_single_reg_req_gp_ecx;
1657  out_infos[3].req = &arch_memory_requirement;
1658 
1659  verify_new_node(res);
1660  return optimize_node(res);
1661 }
1662 
1663 ir_node *new_bd_ia32_CopyB_i(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *mem, unsigned size)
1664 {
1665  static arch_register_req_t const *in_reqs[] = {
1666  &ia32_single_reg_req_gp_edi,
1667  &ia32_single_reg_req_gp_esi,
1668  &arch_memory_requirement,
1669  };
1670 
1671  /* construct in array */
1672  ir_node *const in[] = {
1673  dest,
1674  source,
1675  mem,
1676  };
1677 
1678  ir_graph *const irg = get_irn_irg(block);
1679  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CopyB_i, mode_T, 3, in);
1680 
1681  /* flags */
1682  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1683 
1684  /* init node attributes */
1685  int const n_res = 3;
1686  ia32_copyb_attr_t *const attr = (ia32_copyb_attr_t*)get_irn_generic_attr(res);
1687  (void)attr; /* avoid potential warning */
1688  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1689  init_ia32_copyb_attributes(res, size);
1690  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1691  out_infos[0].req = &ia32_single_reg_req_gp_edi;
1692  out_infos[1].req = &ia32_single_reg_req_gp_esi;
1693  out_infos[2].req = &arch_memory_requirement;
1694 
1695  verify_new_node(res);
1696  return optimize_node(res);
1697 }
1698 
1699 ir_node *new_bd_ia32_CopyEbpEsp(dbg_info *dbgi, ir_node *block, ir_node *ebp)
1700 {
1701  static arch_register_req_t const *in_reqs[] = {
1702  &ia32_single_reg_req_gp_ebp,
1703  };
1704 
1705  /* construct in array */
1706  ir_node *const in[] = {
1707  ebp,
1708  };
1709 
1710  ir_graph *const irg = get_irn_irg(block);
1711  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CopyEbpEsp, ia32_mode_gp, 1, in);
1712 
1713  /* flags */
1714  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1715 
1716  /* init node attributes */
1717  int const n_res = 1;
1718  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1719  (void)attr; /* avoid potential warning */
1720  x86_insn_size_t const size = X86_SIZE_32;
1721  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1722  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1723  out_infos[0].req = &ia32_requirements_gp_esp_I;
1724 
1725  verify_new_node(res);
1726  return optimize_node(res);
1727 }
1728 
1729 ir_node *new_bd_ia32_CvtSI2SD(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1730 {
1731  static arch_register_req_t const *in_reqs[] = {
1732  &ia32_class_reg_req_gp,
1733  &ia32_class_reg_req_gp,
1734  &arch_memory_requirement,
1735  &ia32_class_reg_req_gp,
1736  };
1737 
1738  /* construct in array */
1739  ir_node *const in[] = {
1740  base,
1741  index,
1742  mem,
1743  val,
1744  };
1745 
1746  ir_graph *const irg = get_irn_irg(block);
1747  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CvtSI2SD, ia32_mode_float64, 4, in);
1748 
1749  /* flags */
1750  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1751 
1752  /* init node attributes */
1753  int const n_res = 1;
1754  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1755  (void)attr; /* avoid potential warning */
1756  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1757  set_ia32_am_support(res, ia32_am_unary);
1758  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1759  out_infos[0].req = &ia32_class_reg_req_xmm;
1760 
1761  verify_new_node(res);
1762  return optimize_node(res);
1763 }
1764 
1765 ir_node *new_bd_ia32_CvtSI2SS(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
1766 {
1767  static arch_register_req_t const *in_reqs[] = {
1768  &ia32_class_reg_req_gp,
1769  &ia32_class_reg_req_gp,
1770  &arch_memory_requirement,
1771  &ia32_class_reg_req_gp,
1772  };
1773 
1774  /* construct in array */
1775  ir_node *const in[] = {
1776  base,
1777  index,
1778  mem,
1779  val,
1780  };
1781 
1782  ir_graph *const irg = get_irn_irg(block);
1783  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_CvtSI2SS, ia32_mode_float64, 4, in);
1784 
1785  /* flags */
1786  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1787 
1788  /* init node attributes */
1789  int const n_res = 1;
1790  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1791  (void)attr; /* avoid potential warning */
1792  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1793  set_ia32_am_support(res, ia32_am_unary);
1794  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1795  out_infos[0].req = &ia32_class_reg_req_xmm;
1796 
1797  verify_new_node(res);
1798  return optimize_node(res);
1799 }
1800 
1801 ir_node *new_bd_ia32_Cwtl(dbg_info *dbgi, ir_node *block, ir_node *val)
1802 {
1803  static arch_register_req_t const *in_reqs[] = {
1804  &ia32_single_reg_req_gp_eax,
1805  };
1806 
1807  /* construct in array */
1808  ir_node *const in[] = {
1809  val,
1810  };
1811 
1812  ir_graph *const irg = get_irn_irg(block);
1813  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Cwtl, ia32_mode_gp, 1, in);
1814 
1815  /* flags */
1816  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1817 
1818  /* init node attributes */
1819  int const n_res = 1;
1820  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1821  (void)attr; /* avoid potential warning */
1822  x86_insn_size_t const size = X86_SIZE_32;
1823  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1824  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1825  out_infos[0].req = &ia32_single_reg_req_gp_eax;
1826 
1827  verify_new_node(res);
1828  return optimize_node(res);
1829 }
1830 
1831 ir_node *new_bd_ia32_Dec(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
1832 {
1833  static arch_register_req_t const *in_reqs[] = {
1834  &ia32_class_reg_req_gp,
1835  };
1836 
1837  /* construct in array */
1838  ir_node *const in[] = {
1839  val,
1840  };
1841 
1842  ir_graph *const irg = get_irn_irg(block);
1843  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Dec, ia32_mode_gp, 1, in);
1844 
1845  /* flags */
1846  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1847  irn_flags |= arch_irn_flag_modify_flags;
1848  irn_flags |= arch_irn_flag_rematerializable;
1849 
1850  /* init node attributes */
1851  int const n_res = 2;
1852  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1853  (void)attr; /* avoid potential warning */
1854  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1855  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1856  out_infos[0].req = &ia32_requirements_gp_in_r0;
1857  out_infos[1].req = &ia32_class_reg_req_flags;
1858 
1859  verify_new_node(res);
1860  return optimize_node(res);
1861 }
1862 
1863 ir_node *new_bd_ia32_DecMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
1864 {
1865  static arch_register_req_t const *in_reqs[] = {
1866  &ia32_class_reg_req_gp,
1867  &ia32_class_reg_req_gp,
1868  &arch_memory_requirement,
1869  };
1870 
1871  /* construct in array */
1872  ir_node *const in[] = {
1873  base,
1874  index,
1875  mem,
1876  };
1877 
1878  ir_graph *const irg = get_irn_irg(block);
1879  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_DecMem, mode_T, 3, in);
1880 
1881  /* flags */
1882  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1883  irn_flags |= arch_irn_flag_modify_flags;
1884  irn_flags |= arch_irn_flag_rematerializable;
1885 
1886  /* init node attributes */
1887  int const n_res = 3;
1888  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1889  (void)attr; /* avoid potential warning */
1890  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1891  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1892  out_infos[0].req = &arch_no_requirement;
1893  out_infos[1].req = &ia32_class_reg_req_flags;
1894  out_infos[2].req = &arch_memory_requirement;
1895 
1896  verify_new_node(res);
1897  return optimize_node(res);
1898 }
1899 
1900 ir_node *new_bd_ia32_Div(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high, x86_insn_size_t size)
1901 {
1902  static arch_register_req_t const *in_reqs[] = {
1903  &ia32_class_reg_req_gp,
1904  &ia32_class_reg_req_gp,
1905  &arch_memory_requirement,
1906  &ia32_class_reg_req_gp,
1907  &ia32_single_reg_req_gp_eax,
1908  &ia32_single_reg_req_gp_edx,
1909  };
1910 
1911  /* construct in array */
1912  ir_node *const in[] = {
1913  base,
1914  index,
1915  mem,
1916  divisor,
1917  dividend_low,
1918  dividend_high,
1919  };
1920 
1921  ir_graph *const irg = get_irn_irg(block);
1922  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Div, mode_T, 6, in);
1923 
1924  /* flags */
1925  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1926  irn_flags |= arch_irn_flag_modify_flags;
1927 
1928  /* init node attributes */
1929  int const n_res = 6;
1930  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1931  (void)attr; /* avoid potential warning */
1932  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1933  set_ia32_am_support(res, ia32_am_unary);
1934  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1935  out_infos[0].req = &ia32_single_reg_req_gp_eax;
1936  out_infos[1].req = &ia32_class_reg_req_flags;
1937  out_infos[2].req = &arch_memory_requirement;
1938  out_infos[3].req = &ia32_single_reg_req_gp_edx;
1939  out_infos[4].req = &arch_exec_requirement;
1940  out_infos[5].req = &arch_exec_requirement;
1941 
1942  verify_new_node(res);
1943  return optimize_node(res);
1944 }
1945 
1946 ir_node *new_bd_ia32_Divs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
1947 {
1948  static arch_register_req_t const *in_reqs[] = {
1949  &ia32_class_reg_req_gp,
1950  &ia32_class_reg_req_gp,
1951  &arch_memory_requirement,
1952  &ia32_class_reg_req_xmm,
1953  &ia32_class_reg_req_xmm,
1954  };
1955 
1956  /* construct in array */
1957  ir_node *const in[] = {
1958  base,
1959  index,
1960  mem,
1961  left,
1962  right,
1963  };
1964 
1965  ir_graph *const irg = get_irn_irg(block);
1966  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Divs, mode_T, 5, in);
1967 
1968  /* flags */
1969  arch_irn_flags_t irn_flags = arch_irn_flags_none;
1970  irn_flags |= arch_irn_flag_rematerializable;
1971 
1972  /* init node attributes */
1973  int const n_res = 3;
1974  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
1975  (void)attr; /* avoid potential warning */
1976  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
1977  set_ia32_am_support(res, ia32_am_binary);
1978  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
1979  out_infos[0].req = &ia32_requirements_xmm_in_r3_not_in_r4;
1980  out_infos[1].req = &ia32_class_reg_req_flags;
1981  out_infos[2].req = &arch_memory_requirement;
1982 
1983  verify_new_node(res);
1984  return optimize_node(res);
1985 }
1986 
1987 ir_node *new_bd_ia32_Enter(dbg_info *dbgi, ir_node *block, ir_node *op0)
1988 {
1989  static arch_register_req_t const *in_reqs[] = {
1990  &ia32_single_reg_req_gp_esp,
1991  };
1992 
1993  /* construct in array */
1994  ir_node *const in[] = {
1995  op0,
1996  };
1997 
1998  ir_graph *const irg = get_irn_irg(block);
1999  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Enter, mode_T, 1, in);
2000 
2001  /* flags */
2002  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2003 
2004  /* init node attributes */
2005  int const n_res = 3;
2006  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2007  (void)attr; /* avoid potential warning */
2008  x86_insn_size_t const size = X86_SIZE_32;
2009  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2010  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2011  out_infos[0].req = &ia32_single_reg_req_gp_ebp;
2012  out_infos[1].req = &ia32_requirements_gp_esp_I;
2013  out_infos[2].req = &arch_memory_requirement;
2014 
2015  verify_new_node(res);
2016  return optimize_node(res);
2017 }
2018 
2019 ir_node *new_bd_ia32_FldCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
2020 {
2021  static arch_register_req_t const *in_reqs[] = {
2022  &ia32_class_reg_req_gp,
2023  &ia32_class_reg_req_gp,
2024  &arch_memory_requirement,
2025  };
2026 
2027  /* construct in array */
2028  ir_node *const in[] = {
2029  base,
2030  index,
2031  mem,
2032  };
2033 
2034  ir_graph *const irg = get_irn_irg(block);
2035  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FldCW, ia32_mode_fpcw, 3, in);
2036 
2037  /* flags */
2038  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2039 
2040  /* init node attributes */
2041  int const n_res = 1;
2042  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2043  (void)attr; /* avoid potential warning */
2044  x86_insn_size_t const size = X86_SIZE_16;
2045  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2046  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2047  out_infos[0].req = &ia32_single_reg_req_fp_cw_fpcw;
2048 
2049  verify_new_node(res);
2050  return optimize_node(res);
2051 }
2052 
2053 ir_node *new_bd_ia32_FnstCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *fpcw)
2054 {
2055  static arch_register_req_t const *in_reqs[] = {
2056  &ia32_class_reg_req_gp,
2057  &ia32_class_reg_req_gp,
2058  &arch_memory_requirement,
2059  &ia32_class_reg_req_fp_cw,
2060  };
2061 
2062  /* construct in array */
2063  ir_node *const in[] = {
2064  base,
2065  index,
2066  mem,
2067  fpcw,
2068  };
2069 
2070  ir_graph *const irg = get_irn_irg(block);
2071  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FnstCW, mode_M, 4, in);
2072 
2073  /* flags */
2074  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2075 
2076  /* init node attributes */
2077  int const n_res = 1;
2078  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2079  (void)attr; /* avoid potential warning */
2080  x86_insn_size_t const size = X86_SIZE_16;
2081  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2082  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2083  out_infos[0].req = &arch_memory_requirement;
2084 
2085  verify_new_node(res);
2086  return optimize_node(res);
2087 }
2088 
2089 ir_node *new_bd_ia32_FnstCWNOP(dbg_info *dbgi, ir_node *block, ir_node *fpcw)
2090 {
2091  static arch_register_req_t const *in_reqs[] = {
2092  &ia32_class_reg_req_fp_cw,
2093  };
2094 
2095  /* construct in array */
2096  ir_node *const in[] = {
2097  fpcw,
2098  };
2099 
2100  ir_graph *const irg = get_irn_irg(block);
2101  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FnstCWNOP, mode_M, 1, in);
2102 
2103  /* flags */
2104  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2105 
2106  /* init node attributes */
2107  int const n_res = 1;
2108  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2109  (void)attr; /* avoid potential warning */
2110  x86_insn_size_t const size = X86_SIZE_16;
2111  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2112  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2113  out_infos[0].req = &arch_memory_requirement;
2114 
2115  verify_new_node(res);
2116  return optimize_node(res);
2117 }
2118 
2119 ir_node *new_bd_ia32_FtstFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, bool ins_permuted)
2120 {
2121  static arch_register_req_t const *in_reqs[] = {
2122  &ia32_class_reg_req_fp,
2123  };
2124 
2125  /* construct in array */
2126  ir_node *const in[] = {
2127  left,
2128  };
2129 
2130  ir_graph *const irg = get_irn_irg(block);
2131  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FtstFnstsw, ia32_mode_gp, 1, in);
2132 
2133  /* flags */
2134  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2135 
2136  /* init node attributes */
2137  int const n_res = 1;
2138  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2139  (void)attr; /* avoid potential warning */
2140  x86_insn_size_t const size = X86_SIZE_16; ia32_request_x87_sim(irg);
2141  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2142  attr->ins_permuted = ins_permuted;
2143  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2144  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2145 
2146  verify_new_node(res);
2147  return optimize_node(res);
2148 }
2149 
2150 ir_node *new_bd_ia32_FucomFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted)
2151 {
2152  static arch_register_req_t const *in_reqs[] = {
2153  &ia32_class_reg_req_fp,
2154  &ia32_class_reg_req_fp,
2155  };
2156 
2157  /* construct in array */
2158  ir_node *const in[] = {
2159  left,
2160  right,
2161  };
2162 
2163  ir_graph *const irg = get_irn_irg(block);
2164  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FucomFnstsw, ia32_mode_gp, 2, in);
2165 
2166  /* flags */
2167  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2168 
2169  /* init node attributes */
2170  int const n_res = 1;
2171  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
2172  (void)attr; /* avoid potential warning */
2173  x86_insn_size_t const size = X86_SIZE_16;
2174  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2175  init_ia32_x87_attributes(res);
2176  attr->attr.ins_permuted = ins_permuted;
2177  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2178  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2179 
2180  verify_new_node(res);
2181  return optimize_node(res);
2182 }
2183 
2184 ir_node *new_bd_ia32_Fucomi(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted)
2185 {
2186  static arch_register_req_t const *in_reqs[] = {
2187  &ia32_class_reg_req_fp,
2188  &ia32_class_reg_req_fp,
2189  };
2190 
2191  /* construct in array */
2192  ir_node *const in[] = {
2193  left,
2194  right,
2195  };
2196 
2197  ir_graph *const irg = get_irn_irg(block);
2198  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Fucomi, ia32_mode_flags, 2, in);
2199 
2200  /* flags */
2201  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2202  irn_flags |= arch_irn_flag_rematerializable;
2203 
2204  /* init node attributes */
2205  int const n_res = 1;
2206  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
2207  (void)attr; /* avoid potential warning */
2208  x86_insn_size_t const size = X86_SIZE_80;
2209  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2210  init_ia32_x87_attributes(res);
2211  attr->attr.ins_permuted = ins_permuted;
2212  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2213  out_infos[0].req = &ia32_single_reg_req_flags_eflags;
2214 
2215  verify_new_node(res);
2216  return optimize_node(res);
2217 }
2218 
2219 ir_node *new_bd_ia32_FucomppFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted)
2220 {
2221  static arch_register_req_t const *in_reqs[] = {
2222  &ia32_class_reg_req_fp,
2223  &ia32_class_reg_req_fp,
2224  };
2225 
2226  /* construct in array */
2227  ir_node *const in[] = {
2228  left,
2229  right,
2230  };
2231 
2232  ir_graph *const irg = get_irn_irg(block);
2233  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_FucomppFnstsw, ia32_mode_gp, 2, in);
2234 
2235  /* flags */
2236  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2237 
2238  /* init node attributes */
2239  int const n_res = 1;
2240  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
2241  (void)attr; /* avoid potential warning */
2242  x86_insn_size_t const size = X86_SIZE_32;
2243  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2244  init_ia32_x87_attributes(res);
2245  attr->attr.ins_permuted = ins_permuted;
2246  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2247  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2248 
2249  verify_new_node(res);
2250  return optimize_node(res);
2251 }
2252 
2253 ir_node *new_bd_ia32_GetEIP(dbg_info *dbgi, ir_node *block)
2254 {
2255  arch_register_req_t const **const in_reqs = NULL;
2256 
2257 
2258  ir_graph *const irg = get_irn_irg(block);
2259  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_GetEIP, ia32_mode_gp, 0, NULL);
2260 
2261  /* flags */
2262  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2263 
2264  /* init node attributes */
2265  int const n_res = 1;
2266  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2267  (void)attr; /* avoid potential warning */
2268  x86_insn_size_t const size = X86_SIZE_32;
2269  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2270  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2271  out_infos[0].req = &ia32_class_reg_req_gp;
2272 
2273  verify_new_node(res);
2274  return optimize_node(res);
2275 }
2276 
2277 ir_node *new_bd_ia32_IDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high, x86_insn_size_t size)
2278 {
2279  static arch_register_req_t const *in_reqs[] = {
2280  &ia32_class_reg_req_gp,
2281  &ia32_class_reg_req_gp,
2282  &arch_memory_requirement,
2283  &ia32_class_reg_req_gp,
2284  &ia32_single_reg_req_gp_eax,
2285  &ia32_single_reg_req_gp_edx,
2286  };
2287 
2288  /* construct in array */
2289  ir_node *const in[] = {
2290  base,
2291  index,
2292  mem,
2293  divisor,
2294  dividend_low,
2295  dividend_high,
2296  };
2297 
2298  ir_graph *const irg = get_irn_irg(block);
2299  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IDiv, mode_T, 6, in);
2300 
2301  /* flags */
2302  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2303  irn_flags |= arch_irn_flag_modify_flags;
2304 
2305  /* init node attributes */
2306  int const n_res = 6;
2307  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2308  (void)attr; /* avoid potential warning */
2309  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2310  set_ia32_am_support(res, ia32_am_unary);
2311  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2312  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2313  out_infos[1].req = &ia32_class_reg_req_flags;
2314  out_infos[2].req = &arch_memory_requirement;
2315  out_infos[3].req = &ia32_single_reg_req_gp_edx;
2316  out_infos[4].req = &arch_exec_requirement;
2317  out_infos[5].req = &arch_exec_requirement;
2318 
2319  verify_new_node(res);
2320  return optimize_node(res);
2321 }
2322 
2323 ir_node *new_bd_ia32_IJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *target)
2324 {
2325  static arch_register_req_t const *in_reqs[] = {
2326  &ia32_class_reg_req_gp,
2327  &ia32_class_reg_req_gp,
2328  &arch_memory_requirement,
2329  &ia32_class_reg_req_gp,
2330  };
2331 
2332  /* construct in array */
2333  ir_node *const in[] = {
2334  base,
2335  index,
2336  mem,
2337  target,
2338  };
2339 
2340  ir_graph *const irg = get_irn_irg(block);
2341  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IJmp, mode_X, 4, in);
2342 
2343  /* flags */
2344  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2345 
2346  /* init node attributes */
2347  int const n_res = 3;
2348  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2349  (void)attr; /* avoid potential warning */
2350  x86_insn_size_t const size = X86_SIZE_32;
2351  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2352  set_ia32_am_support(res, ia32_am_unary);
2353  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2354  out_infos[0].req = &arch_exec_requirement;
2355  out_infos[1].req = &arch_no_requirement;
2356  out_infos[2].req = &arch_memory_requirement;
2357 
2358  verify_new_node(res);
2359  return optimize_node(res);
2360 }
2361 
2362 ir_node *new_bd_ia32_IMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2363 {
2364  static arch_register_req_t const *in_reqs[] = {
2365  &ia32_class_reg_req_gp,
2366  &ia32_class_reg_req_gp,
2367  &arch_memory_requirement,
2368  &ia32_class_reg_req_gp,
2369  &ia32_class_reg_req_gp,
2370  };
2371 
2372  /* construct in array */
2373  ir_node *const in[] = {
2374  base,
2375  index,
2376  mem,
2377  left,
2378  right,
2379  };
2380 
2381  ir_graph *const irg = get_irn_irg(block);
2382  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IMul, ia32_mode_gp, 5, in);
2383 
2384  /* flags */
2385  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2386  irn_flags |= arch_irn_flag_modify_flags;
2387  irn_flags |= arch_irn_flag_rematerializable;
2388 
2389  /* init node attributes */
2390  int const n_res = 3;
2391  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2392  (void)attr; /* avoid potential warning */
2393  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2394  set_ia32_am_support(res, ia32_am_binary);
2395  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2396  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
2397  out_infos[1].req = &ia32_class_reg_req_flags;
2398  out_infos[2].req = &arch_memory_requirement;
2399 
2400  verify_new_node(res);
2401  return optimize_node(res);
2402 }
2403 
2404 ir_node *new_bd_ia32_IMul_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2405 {
2406  static arch_register_req_t const *in_reqs[] = {
2407  &ia32_class_reg_req_gp,
2408  &ia32_class_reg_req_gp,
2409  &arch_memory_requirement,
2410  &ia32_requirements_gp_eax_ebx_ecx_edx,
2411  &ia32_requirements_gp_eax_ebx_ecx_edx,
2412  };
2413 
2414  /* construct in array */
2415  ir_node *const in[] = {
2416  base,
2417  index,
2418  mem,
2419  left,
2420  right,
2421  };
2422 
2423  ir_graph *const irg = get_irn_irg(block);
2424  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IMul, ia32_mode_gp, 5, in);
2425 
2426  /* flags */
2427  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2428  irn_flags |= arch_irn_flag_modify_flags;
2429  irn_flags |= arch_irn_flag_rematerializable;
2430 
2431  /* init node attributes */
2432  int const n_res = 3;
2433  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2434  (void)attr; /* avoid potential warning */
2435  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2436  set_ia32_am_support(res, ia32_am_binary);
2437  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2438  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
2439  out_infos[1].req = &ia32_class_reg_req_flags;
2440  out_infos[2].req = &arch_memory_requirement;
2441 
2442  verify_new_node(res);
2443  return optimize_node(res);
2444 }
2445 
2446 ir_node *new_bd_ia32_IMul1OP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2447 {
2448  static arch_register_req_t const *in_reqs[] = {
2449  &ia32_class_reg_req_gp,
2450  &ia32_class_reg_req_gp,
2451  &arch_memory_requirement,
2452  &ia32_single_reg_req_gp_eax,
2453  &ia32_class_reg_req_gp,
2454  };
2455 
2456  /* construct in array */
2457  ir_node *const in[] = {
2458  base,
2459  index,
2460  mem,
2461  left,
2462  right,
2463  };
2464 
2465  ir_graph *const irg = get_irn_irg(block);
2466  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IMul1OP, mode_T, 5, in);
2467 
2468  /* flags */
2469  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2470  irn_flags |= arch_irn_flag_modify_flags;
2471 
2472  /* init node attributes */
2473  int const n_res = 4;
2474  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2475  (void)attr; /* avoid potential warning */
2476  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2477  set_ia32_am_support(res, ia32_am_binary);
2478  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2479  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2480  out_infos[1].req = &ia32_class_reg_req_flags;
2481  out_infos[2].req = &arch_memory_requirement;
2482  out_infos[3].req = &ia32_single_reg_req_gp_edx;
2483 
2484  verify_new_node(res);
2485  return optimize_node(res);
2486 }
2487 
2488 ir_node *new_bd_ia32_IMulImm(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2489 {
2490  static arch_register_req_t const *in_reqs[] = {
2491  &ia32_class_reg_req_gp,
2492  &ia32_class_reg_req_gp,
2493  &arch_memory_requirement,
2494  &ia32_class_reg_req_gp,
2495  &ia32_class_reg_req_gp,
2496  };
2497 
2498  /* construct in array */
2499  ir_node *const in[] = {
2500  base,
2501  index,
2502  mem,
2503  left,
2504  right,
2505  };
2506 
2507  ir_graph *const irg = get_irn_irg(block);
2508  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IMulImm, ia32_mode_gp, 5, in);
2509 
2510  /* flags */
2511  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2512  irn_flags |= arch_irn_flag_modify_flags;
2513  irn_flags |= arch_irn_flag_rematerializable;
2514 
2515  /* init node attributes */
2516  int const n_res = 3;
2517  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2518  (void)attr; /* avoid potential warning */
2519  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2520  set_ia32_am_support(res, ia32_am_binary);
2521  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2522  out_infos[0].req = &ia32_class_reg_req_gp;
2523  out_infos[1].req = &ia32_class_reg_req_flags;
2524  out_infos[2].req = &arch_memory_requirement;
2525 
2526  verify_new_node(res);
2527  return optimize_node(res);
2528 }
2529 
2530 ir_node *new_bd_ia32_Immediate(dbg_info *dbgi, ir_node *block, const x86_imm32_t *imm)
2531 {
2532  arch_register_req_t const **const in_reqs = NULL;
2533 
2534 
2535  ir_graph *const irg = get_irn_irg(block);
2536  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Immediate, ia32_mode_gp, 0, NULL);
2537 
2538  /* flags */
2539  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2540  irn_flags |= arch_irn_flag_not_scheduled;
2541 
2542  /* init node attributes */
2543  int const n_res = 1;
2544  ia32_immediate_attr_t *const attr = (ia32_immediate_attr_t*)get_irn_generic_attr(res);
2545  (void)attr; /* avoid potential warning */
2546  x86_insn_size_t const size = X86_SIZE_32;
2547  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2548  init_ia32_immediate_attributes(res, imm);
2549  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2550  out_infos[0].req = &ia32_requirements_gp_gp_NOREG_I;
2551 
2552  verify_new_node(res);
2553  return optimize_node(res);
2554 }
2555 
2556 ir_node *new_bd_ia32_Inc(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
2557 {
2558  static arch_register_req_t const *in_reqs[] = {
2559  &ia32_class_reg_req_gp,
2560  };
2561 
2562  /* construct in array */
2563  ir_node *const in[] = {
2564  val,
2565  };
2566 
2567  ir_graph *const irg = get_irn_irg(block);
2568  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Inc, ia32_mode_gp, 1, in);
2569 
2570  /* flags */
2571  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2572  irn_flags |= arch_irn_flag_modify_flags;
2573  irn_flags |= arch_irn_flag_rematerializable;
2574 
2575  /* init node attributes */
2576  int const n_res = 2;
2577  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2578  (void)attr; /* avoid potential warning */
2579  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2580  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2581  out_infos[0].req = &ia32_requirements_gp_in_r0;
2582  out_infos[1].req = &ia32_class_reg_req_flags;
2583 
2584  verify_new_node(res);
2585  return optimize_node(res);
2586 }
2587 
2588 ir_node *new_bd_ia32_IncMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
2589 {
2590  static arch_register_req_t const *in_reqs[] = {
2591  &ia32_class_reg_req_gp,
2592  &ia32_class_reg_req_gp,
2593  &arch_memory_requirement,
2594  };
2595 
2596  /* construct in array */
2597  ir_node *const in[] = {
2598  base,
2599  index,
2600  mem,
2601  };
2602 
2603  ir_graph *const irg = get_irn_irg(block);
2604  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_IncMem, mode_T, 3, in);
2605 
2606  /* flags */
2607  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2608  irn_flags |= arch_irn_flag_modify_flags;
2609  irn_flags |= arch_irn_flag_rematerializable;
2610 
2611  /* init node attributes */
2612  int const n_res = 3;
2613  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2614  (void)attr; /* avoid potential warning */
2615  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2616  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2617  out_infos[0].req = &arch_no_requirement;
2618  out_infos[1].req = &ia32_class_reg_req_flags;
2619  out_infos[2].req = &arch_memory_requirement;
2620 
2621  verify_new_node(res);
2622  return optimize_node(res);
2623 }
2624 
2625 ir_node *new_bd_ia32_Inport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *mem, x86_insn_size_t size)
2626 {
2627  static arch_register_req_t const *in_reqs[] = {
2628  &ia32_single_reg_req_gp_edx,
2629  &arch_memory_requirement,
2630  };
2631 
2632  /* construct in array */
2633  ir_node *const in[] = {
2634  port,
2635  mem,
2636  };
2637 
2638  ir_graph *const irg = get_irn_irg(block);
2639  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Inport, mode_T, 2, in);
2640 
2641  /* flags */
2642  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2643  irn_flags |= arch_irn_flag_rematerializable;
2644 
2645  /* init node attributes */
2646  int const n_res = 2;
2647  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2648  (void)attr; /* avoid potential warning */
2649  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2650  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2651  out_infos[0].req = &ia32_single_reg_req_gp_eax;
2652  out_infos[1].req = &arch_memory_requirement;
2653 
2654  verify_new_node(res);
2655  return optimize_node(res);
2656 }
2657 
2658 ir_node *new_bd_ia32_Jcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, x86_condition_code_t condition_code)
2659 {
2660  static arch_register_req_t const *in_reqs[] = {
2661  &ia32_single_reg_req_flags_eflags,
2662  };
2663 
2664  /* construct in array */
2665  ir_node *const in[] = {
2666  eflags,
2667  };
2668 
2669  ir_graph *const irg = get_irn_irg(block);
2670  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Jcc, mode_T, 1, in);
2671 
2672  /* flags */
2673  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2674 
2675  /* init node attributes */
2676  int const n_res = 2;
2677  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
2678  (void)attr; /* avoid potential warning */
2679  x86_insn_size_t const size = X86_SIZE_32;
2680  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2681  init_ia32_condcode_attributes(res, condition_code);
2682  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2683  out_infos[0].req = &arch_exec_requirement;
2684  out_infos[1].req = &arch_exec_requirement;
2685 
2686  verify_new_node(res);
2687  return optimize_node(res);
2688 }
2689 
2690 ir_node *new_bd_ia32_Jmp(dbg_info *dbgi, ir_node *block)
2691 {
2692  arch_register_req_t const **const in_reqs = NULL;
2693 
2694 
2695  ir_graph *const irg = get_irn_irg(block);
2696  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Jmp, mode_X, 0, NULL);
2697 
2698  /* flags */
2699  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2700  irn_flags |= arch_irn_flag_simple_jump;
2701 
2702  /* init node attributes */
2703  int const n_res = 1;
2704  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2705  (void)attr; /* avoid potential warning */
2706  x86_insn_size_t const size = X86_SIZE_32;
2707  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2708  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2709  out_infos[0].req = &arch_exec_requirement;
2710 
2711  verify_new_node(res);
2712  return optimize_node(res);
2713 }
2714 
2715 ir_node *new_bd_ia32_LdTls(dbg_info *dbgi, ir_node *block)
2716 {
2717  arch_register_req_t const **const in_reqs = NULL;
2718 
2719 
2720  ir_graph *const irg = get_irn_irg(block);
2721  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_LdTls, ia32_mode_gp, 0, NULL);
2722 
2723  /* flags */
2724  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2725  irn_flags |= arch_irn_flag_rematerializable;
2726 
2727  /* init node attributes */
2728  int const n_res = 1;
2729  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2730  (void)attr; /* avoid potential warning */
2731  x86_insn_size_t const size = X86_SIZE_32;
2732  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2733  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2734  out_infos[0].req = &ia32_class_reg_req_gp;
2735 
2736  verify_new_node(res);
2737  return optimize_node(res);
2738 }
2739 
2740 ir_node *new_bd_ia32_Lea(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index)
2741 {
2742  static arch_register_req_t const *in_reqs[] = {
2743  &ia32_class_reg_req_gp,
2744  &ia32_class_reg_req_gp,
2745  };
2746 
2747  /* construct in array */
2748  ir_node *const in[] = {
2749  base,
2750  index,
2751  };
2752 
2753  ir_graph *const irg = get_irn_irg(block);
2754  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Lea, ia32_mode_gp, 2, in);
2755 
2756  /* flags */
2757  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2758  irn_flags |= arch_irn_flag_modify_flags;
2759  irn_flags |= arch_irn_flag_rematerializable;
2760 
2761  /* init node attributes */
2762  int const n_res = 1;
2763  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2764  (void)attr; /* avoid potential warning */
2765  x86_insn_size_t const size = X86_SIZE_32;
2766  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2767  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2768  out_infos[0].req = &ia32_class_reg_req_gp;
2769 
2770  verify_new_node(res);
2771  return optimize_node(res);
2772 }
2773 
2774 ir_node *new_bd_ia32_Leave(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1)
2775 {
2776  static arch_register_req_t const *in_reqs[] = {
2777  &arch_memory_requirement,
2778  &ia32_single_reg_req_gp_ebp,
2779  };
2780 
2781  /* construct in array */
2782  ir_node *const in[] = {
2783  op0,
2784  op1,
2785  };
2786 
2787  ir_graph *const irg = get_irn_irg(block);
2788  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Leave, mode_T, 2, in);
2789 
2790  /* flags */
2791  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2792 
2793  /* init node attributes */
2794  int const n_res = 3;
2795  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2796  (void)attr; /* avoid potential warning */
2797  x86_insn_size_t const size = X86_SIZE_32;
2798  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2799  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2800  out_infos[0].req = &ia32_requirements_gp_ebp_I;
2801  out_infos[1].req = &arch_memory_requirement;
2802  out_infos[2].req = &ia32_requirements_gp_esp_I;
2803 
2804  verify_new_node(res);
2805  return optimize_node(res);
2806 }
2807 
2808 ir_node *new_bd_ia32_Load(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size, bool sign_extend)
2809 {
2810  static arch_register_req_t const *in_reqs[] = {
2811  &ia32_class_reg_req_gp,
2812  &ia32_class_reg_req_gp,
2813  &arch_memory_requirement,
2814  };
2815 
2816  /* construct in array */
2817  ir_node *const in[] = {
2818  base,
2819  index,
2820  mem,
2821  };
2822 
2823  ir_graph *const irg = get_irn_irg(block);
2824  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Load, mode_T, 3, in);
2825 
2826  /* flags */
2827  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2828 
2829  /* init node attributes */
2830  int const n_res = 5;
2831  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2832  (void)attr; /* avoid potential warning */
2833  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2834  attr->sign_extend = sign_extend;
2835  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2836  out_infos[0].req = &ia32_class_reg_req_gp;
2837  out_infos[1].req = &arch_no_requirement;
2838  out_infos[2].req = &arch_memory_requirement;
2839  out_infos[3].req = &arch_exec_requirement;
2840  out_infos[4].req = &arch_exec_requirement;
2841 
2842  verify_new_node(res);
2843  return optimize_node(res);
2844 }
2845 
2846 ir_node *new_bd_ia32_Maxs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2847 {
2848  static arch_register_req_t const *in_reqs[] = {
2849  &ia32_class_reg_req_gp,
2850  &ia32_class_reg_req_gp,
2851  &arch_memory_requirement,
2852  &ia32_class_reg_req_xmm,
2853  &ia32_class_reg_req_xmm,
2854  };
2855 
2856  /* construct in array */
2857  ir_node *const in[] = {
2858  base,
2859  index,
2860  mem,
2861  left,
2862  right,
2863  };
2864 
2865  ir_graph *const irg = get_irn_irg(block);
2866  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Maxs, ia32_mode_float64, 5, in);
2867 
2868  /* flags */
2869  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2870  irn_flags |= arch_irn_flag_rematerializable;
2871 
2872  /* init node attributes */
2873  int const n_res = 3;
2874  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2875  (void)attr; /* avoid potential warning */
2876  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2877  set_ia32_am_support(res, ia32_am_binary);
2878  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2879  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
2880  out_infos[1].req = &ia32_class_reg_req_flags;
2881  out_infos[2].req = &arch_memory_requirement;
2882 
2883  verify_new_node(res);
2884  return optimize_node(res);
2885 }
2886 
2887 ir_node *new_bd_ia32_Mins(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2888 {
2889  static arch_register_req_t const *in_reqs[] = {
2890  &ia32_class_reg_req_gp,
2891  &ia32_class_reg_req_gp,
2892  &arch_memory_requirement,
2893  &ia32_class_reg_req_xmm,
2894  &ia32_class_reg_req_xmm,
2895  };
2896 
2897  /* construct in array */
2898  ir_node *const in[] = {
2899  base,
2900  index,
2901  mem,
2902  left,
2903  right,
2904  };
2905 
2906  ir_graph *const irg = get_irn_irg(block);
2907  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Mins, ia32_mode_float64, 5, in);
2908 
2909  /* flags */
2910  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2911  irn_flags |= arch_irn_flag_rematerializable;
2912 
2913  /* init node attributes */
2914  int const n_res = 3;
2915  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2916  (void)attr; /* avoid potential warning */
2917  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2918  set_ia32_am_support(res, ia32_am_binary);
2919  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2920  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
2921  out_infos[1].req = &ia32_class_reg_req_flags;
2922  out_infos[2].req = &arch_memory_requirement;
2923 
2924  verify_new_node(res);
2925  return optimize_node(res);
2926 }
2927 
2928 ir_node *new_bd_ia32_Minus64(dbg_info *dbgi, ir_node *block, ir_node *low, ir_node *high)
2929 {
2930  static arch_register_req_t const *in_reqs[] = {
2931  &ia32_class_reg_req_gp,
2932  &ia32_class_reg_req_gp,
2933  };
2934 
2935  /* construct in array */
2936  ir_node *const in[] = {
2937  low,
2938  high,
2939  };
2940 
2941  ir_graph *const irg = get_irn_irg(block);
2942  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Minus64, mode_T, 2, in);
2943 
2944  /* flags */
2945  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2946  irn_flags |= arch_irn_flag_modify_flags;
2947  irn_flags |= arch_irn_flag_rematerializable;
2948 
2949  /* init node attributes */
2950  int const n_res = 2;
2951  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2952  (void)attr; /* avoid potential warning */
2953  x86_insn_size_t const size = X86_SIZE_32;
2954  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2955  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2956  out_infos[0].req = &ia32_requirements_gp_in_r0;
2957  out_infos[1].req = &ia32_requirements_gp_in_r1;
2958 
2959  verify_new_node(res);
2960  return optimize_node(res);
2961 }
2962 
2963 ir_node *new_bd_ia32_Movd(dbg_info *dbgi, ir_node *block, ir_node *op0)
2964 {
2965  static arch_register_req_t const *in_reqs[] = {
2966  &ia32_class_reg_req_gp,
2967  };
2968 
2969  /* construct in array */
2970  ir_node *const in[] = {
2971  op0,
2972  };
2973 
2974  ir_graph *const irg = get_irn_irg(block);
2975  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Movd, ia32_mode_float64, 1, in);
2976 
2977  /* flags */
2978  arch_irn_flags_t irn_flags = arch_irn_flags_none;
2979  irn_flags |= arch_irn_flag_rematerializable;
2980 
2981  /* init node attributes */
2982  int const n_res = 1;
2983  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
2984  (void)attr; /* avoid potential warning */
2985  x86_insn_size_t const size = X86_SIZE_32;
2986  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
2987  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
2988  out_infos[0].req = &ia32_class_reg_req_xmm;
2989 
2990  verify_new_node(res);
2991  return optimize_node(res);
2992 }
2993 
2994 ir_node *new_bd_ia32_Mul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
2995 {
2996  static arch_register_req_t const *in_reqs[] = {
2997  &ia32_class_reg_req_gp,
2998  &ia32_class_reg_req_gp,
2999  &arch_memory_requirement,
3000  &ia32_single_reg_req_gp_eax,
3001  &ia32_class_reg_req_gp,
3002  };
3003 
3004  /* construct in array */
3005  ir_node *const in[] = {
3006  base,
3007  index,
3008  mem,
3009  left,
3010  right,
3011  };
3012 
3013  ir_graph *const irg = get_irn_irg(block);
3014  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Mul, mode_T, 5, in);
3015 
3016  /* flags */
3017  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3018  irn_flags |= arch_irn_flag_modify_flags;
3019 
3020  /* init node attributes */
3021  int const n_res = 4;
3022  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3023  (void)attr; /* avoid potential warning */
3024  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3025  set_ia32_am_support(res, ia32_am_binary);
3026  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3027  out_infos[0].req = &ia32_single_reg_req_gp_eax;
3028  out_infos[1].req = &ia32_class_reg_req_flags;
3029  out_infos[2].req = &arch_memory_requirement;
3030  out_infos[3].req = &ia32_single_reg_req_gp_edx;
3031 
3032  verify_new_node(res);
3033  return optimize_node(res);
3034 }
3035 
3036 ir_node *new_bd_ia32_Muls(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3037 {
3038  static arch_register_req_t const *in_reqs[] = {
3039  &ia32_class_reg_req_gp,
3040  &ia32_class_reg_req_gp,
3041  &arch_memory_requirement,
3042  &ia32_class_reg_req_xmm,
3043  &ia32_class_reg_req_xmm,
3044  };
3045 
3046  /* construct in array */
3047  ir_node *const in[] = {
3048  base,
3049  index,
3050  mem,
3051  left,
3052  right,
3053  };
3054 
3055  ir_graph *const irg = get_irn_irg(block);
3056  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Muls, ia32_mode_float64, 5, in);
3057 
3058  /* flags */
3059  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3060  irn_flags |= arch_irn_flag_rematerializable;
3061 
3062  /* init node attributes */
3063  int const n_res = 3;
3064  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3065  (void)attr; /* avoid potential warning */
3066  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3067  set_ia32_am_support(res, ia32_am_binary);
3068  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3069  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
3070  out_infos[1].req = &ia32_class_reg_req_flags;
3071  out_infos[2].req = &arch_memory_requirement;
3072 
3073  verify_new_node(res);
3074  return optimize_node(res);
3075 }
3076 
3077 ir_node *new_bd_ia32_Neg(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
3078 {
3079  static arch_register_req_t const *in_reqs[] = {
3080  &ia32_class_reg_req_gp,
3081  };
3082 
3083  /* construct in array */
3084  ir_node *const in[] = {
3085  val,
3086  };
3087 
3088  ir_graph *const irg = get_irn_irg(block);
3089  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Neg, ia32_mode_gp, 1, in);
3090 
3091  /* flags */
3092  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3093  irn_flags |= arch_irn_flag_modify_flags;
3094  irn_flags |= arch_irn_flag_rematerializable;
3095 
3096  /* init node attributes */
3097  int const n_res = 2;
3098  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3099  (void)attr; /* avoid potential warning */
3100  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3101  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3102  out_infos[0].req = &ia32_requirements_gp_in_r0;
3103  out_infos[1].req = &ia32_class_reg_req_flags;
3104 
3105  verify_new_node(res);
3106  return optimize_node(res);
3107 }
3108 
3109 ir_node *new_bd_ia32_NegMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
3110 {
3111  static arch_register_req_t const *in_reqs[] = {
3112  &ia32_class_reg_req_gp,
3113  &ia32_class_reg_req_gp,
3114  &arch_memory_requirement,
3115  };
3116 
3117  /* construct in array */
3118  ir_node *const in[] = {
3119  base,
3120  index,
3121  mem,
3122  };
3123 
3124  ir_graph *const irg = get_irn_irg(block);
3125  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NegMem, mode_T, 3, in);
3126 
3127  /* flags */
3128  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3129  irn_flags |= arch_irn_flag_modify_flags;
3130  irn_flags |= arch_irn_flag_rematerializable;
3131 
3132  /* init node attributes */
3133  int const n_res = 3;
3134  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3135  (void)attr; /* avoid potential warning */
3136  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3137  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3138  out_infos[0].req = &arch_no_requirement;
3139  out_infos[1].req = &ia32_class_reg_req_flags;
3140  out_infos[2].req = &arch_memory_requirement;
3141 
3142  verify_new_node(res);
3143  return optimize_node(res);
3144 }
3145 
3146 ir_node *new_bd_ia32_NoReg_FP(dbg_info *dbgi, ir_node *block)
3147 {
3148  arch_register_req_t const **const in_reqs = NULL;
3149 
3150 
3151  ir_graph *const irg = get_irn_irg(block);
3152  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NoReg_FP, x86_mode_E, 0, NULL);
3153 
3154  /* flags */
3155  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3156  irn_flags |= arch_irn_flag_not_scheduled;
3157 
3158  /* init node attributes */
3159  int const n_res = 1;
3160  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3161  (void)attr; /* avoid potential warning */
3162  x86_insn_size_t const size = X86_SIZE_32;
3163  ia32_request_x87_sim(irg);
3164  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3165  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3166  out_infos[0].req = &ia32_requirements_fp_fp_NOREG_I;
3167 
3168  verify_new_node(res);
3169  return optimize_node(res);
3170 }
3171 
3172 ir_node *new_bd_ia32_NoReg_GP(dbg_info *dbgi, ir_node *block)
3173 {
3174  arch_register_req_t const **const in_reqs = NULL;
3175 
3176 
3177  ir_graph *const irg = get_irn_irg(block);
3178  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NoReg_GP, ia32_mode_gp, 0, NULL);
3179 
3180  /* flags */
3181  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3182  irn_flags |= arch_irn_flag_not_scheduled;
3183 
3184  /* init node attributes */
3185  int const n_res = 1;
3186  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3187  (void)attr; /* avoid potential warning */
3188  x86_insn_size_t const size = X86_SIZE_32;
3189  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3190  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3191  out_infos[0].req = &ia32_requirements_gp_gp_NOREG_I;
3192 
3193  verify_new_node(res);
3194  return optimize_node(res);
3195 }
3196 
3197 ir_node *new_bd_ia32_NoReg_XMM(dbg_info *dbgi, ir_node *block)
3198 {
3199  arch_register_req_t const **const in_reqs = NULL;
3200 
3201 
3202  ir_graph *const irg = get_irn_irg(block);
3203  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NoReg_XMM, ia32_mode_float64, 0, NULL);
3204 
3205  /* flags */
3206  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3207  irn_flags |= arch_irn_flag_not_scheduled;
3208 
3209  /* init node attributes */
3210  int const n_res = 1;
3211  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3212  (void)attr; /* avoid potential warning */
3213  x86_insn_size_t const size = X86_SIZE_32;
3214  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3215  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3216  out_infos[0].req = &ia32_requirements_xmm_xmm_NOREG_I;
3217 
3218  verify_new_node(res);
3219  return optimize_node(res);
3220 }
3221 
3222 ir_node *new_bd_ia32_Not(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
3223 {
3224  static arch_register_req_t const *in_reqs[] = {
3225  &ia32_class_reg_req_gp,
3226  };
3227 
3228  /* construct in array */
3229  ir_node *const in[] = {
3230  val,
3231  };
3232 
3233  ir_graph *const irg = get_irn_irg(block);
3234  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Not, ia32_mode_gp, 1, in);
3235 
3236  /* flags */
3237  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3238  irn_flags |= arch_irn_flag_rematerializable;
3239 
3240  /* init node attributes */
3241  int const n_res = 1;
3242  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3243  (void)attr; /* avoid potential warning */
3244  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3245  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3246  out_infos[0].req = &ia32_requirements_gp_in_r0;
3247 
3248  verify_new_node(res);
3249  return optimize_node(res);
3250 }
3251 
3252 ir_node *new_bd_ia32_Not_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, x86_insn_size_t size)
3253 {
3254  static arch_register_req_t const *in_reqs[] = {
3255  &ia32_requirements_gp_eax_ebx_ecx_edx,
3256  };
3257 
3258  /* construct in array */
3259  ir_node *const in[] = {
3260  val,
3261  };
3262 
3263  ir_graph *const irg = get_irn_irg(block);
3264  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Not, ia32_mode_gp, 1, in);
3265 
3266  /* flags */
3267  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3268  irn_flags |= arch_irn_flag_rematerializable;
3269 
3270  /* init node attributes */
3271  int const n_res = 1;
3272  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3273  (void)attr; /* avoid potential warning */
3274  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3275  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3276  out_infos[0].req = &ia32_requirements_gp_in_r0;
3277 
3278  verify_new_node(res);
3279  return optimize_node(res);
3280 }
3281 
3282 ir_node *new_bd_ia32_NotMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
3283 {
3284  static arch_register_req_t const *in_reqs[] = {
3285  &ia32_class_reg_req_gp,
3286  &ia32_class_reg_req_gp,
3287  &arch_memory_requirement,
3288  };
3289 
3290  /* construct in array */
3291  ir_node *const in[] = {
3292  base,
3293  index,
3294  mem,
3295  };
3296 
3297  ir_graph *const irg = get_irn_irg(block);
3298  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_NotMem, mode_T, 3, in);
3299 
3300  /* flags */
3301  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3302  irn_flags |= arch_irn_flag_rematerializable;
3303 
3304  /* init node attributes */
3305  int const n_res = 3;
3306  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3307  (void)attr; /* avoid potential warning */
3308  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3309  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3310  out_infos[0].req = &arch_no_requirement;
3311  out_infos[1].req = &arch_no_requirement;
3312  out_infos[2].req = &arch_memory_requirement;
3313 
3314  verify_new_node(res);
3315  return optimize_node(res);
3316 }
3317 
3318 ir_node *new_bd_ia32_Or(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3319 {
3320  static arch_register_req_t const *in_reqs[] = {
3321  &ia32_class_reg_req_gp,
3322  &ia32_class_reg_req_gp,
3323  &arch_memory_requirement,
3324  &ia32_class_reg_req_gp,
3325  &ia32_class_reg_req_gp,
3326  };
3327 
3328  /* construct in array */
3329  ir_node *const in[] = {
3330  base,
3331  index,
3332  mem,
3333  left,
3334  right,
3335  };
3336 
3337  ir_graph *const irg = get_irn_irg(block);
3338  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Or, ia32_mode_gp, 5, in);
3339 
3340  /* flags */
3341  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3342  irn_flags |= arch_irn_flag_modify_flags;
3343  irn_flags |= arch_irn_flag_rematerializable;
3344 
3345  /* init node attributes */
3346  int const n_res = 3;
3347  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3348  (void)attr; /* avoid potential warning */
3349  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3350  set_ia32_am_support(res, ia32_am_binary);
3351  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3352  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
3353  out_infos[1].req = &ia32_class_reg_req_flags;
3354  out_infos[2].req = &arch_memory_requirement;
3355 
3356  verify_new_node(res);
3357  return optimize_node(res);
3358 }
3359 
3360 ir_node *new_bd_ia32_Or_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3361 {
3362  static arch_register_req_t const *in_reqs[] = {
3363  &ia32_class_reg_req_gp,
3364  &ia32_class_reg_req_gp,
3365  &arch_memory_requirement,
3366  &ia32_requirements_gp_eax_ebx_ecx_edx,
3367  &ia32_requirements_gp_eax_ebx_ecx_edx,
3368  };
3369 
3370  /* construct in array */
3371  ir_node *const in[] = {
3372  base,
3373  index,
3374  mem,
3375  left,
3376  right,
3377  };
3378 
3379  ir_graph *const irg = get_irn_irg(block);
3380  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Or, ia32_mode_gp, 5, in);
3381 
3382  /* flags */
3383  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3384  irn_flags |= arch_irn_flag_modify_flags;
3385  irn_flags |= arch_irn_flag_rematerializable;
3386 
3387  /* init node attributes */
3388  int const n_res = 3;
3389  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3390  (void)attr; /* avoid potential warning */
3391  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3392  set_ia32_am_support(res, ia32_am_binary);
3393  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3394  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
3395  out_infos[1].req = &ia32_class_reg_req_flags;
3396  out_infos[2].req = &arch_memory_requirement;
3397 
3398  verify_new_node(res);
3399  return optimize_node(res);
3400 }
3401 
3402 ir_node *new_bd_ia32_OrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
3403 {
3404  static arch_register_req_t const *in_reqs[] = {
3405  &ia32_class_reg_req_gp,
3406  &ia32_class_reg_req_gp,
3407  &arch_memory_requirement,
3408  &ia32_class_reg_req_gp,
3409  };
3410 
3411  /* construct in array */
3412  ir_node *const in[] = {
3413  base,
3414  index,
3415  mem,
3416  val,
3417  };
3418 
3419  ir_graph *const irg = get_irn_irg(block);
3420  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_OrMem, mode_T, 4, in);
3421 
3422  /* flags */
3423  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3424  irn_flags |= arch_irn_flag_modify_flags;
3425  irn_flags |= arch_irn_flag_rematerializable;
3426 
3427  /* init node attributes */
3428  int const n_res = 3;
3429  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3430  (void)attr; /* avoid potential warning */
3431  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3432  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3433  out_infos[0].req = &arch_no_requirement;
3434  out_infos[1].req = &ia32_class_reg_req_flags;
3435  out_infos[2].req = &arch_memory_requirement;
3436 
3437  verify_new_node(res);
3438  return optimize_node(res);
3439 }
3440 
3441 ir_node *new_bd_ia32_OrMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
3442 {
3443  static arch_register_req_t const *in_reqs[] = {
3444  &ia32_class_reg_req_gp,
3445  &ia32_class_reg_req_gp,
3446  &arch_memory_requirement,
3447  &ia32_requirements_gp_eax_ebx_ecx_edx,
3448  };
3449 
3450  /* construct in array */
3451  ir_node *const in[] = {
3452  base,
3453  index,
3454  mem,
3455  val,
3456  };
3457 
3458  ir_graph *const irg = get_irn_irg(block);
3459  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_OrMem, mode_T, 4, in);
3460 
3461  /* flags */
3462  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3463  irn_flags |= arch_irn_flag_modify_flags;
3464  irn_flags |= arch_irn_flag_rematerializable;
3465 
3466  /* init node attributes */
3467  int const n_res = 3;
3468  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3469  (void)attr; /* avoid potential warning */
3470  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3471  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3472  out_infos[0].req = &arch_no_requirement;
3473  out_infos[1].req = &ia32_class_reg_req_flags;
3474  out_infos[2].req = &arch_memory_requirement;
3475 
3476  verify_new_node(res);
3477  return optimize_node(res);
3478 }
3479 
3480 ir_node *new_bd_ia32_Orp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
3481 {
3482  static arch_register_req_t const *in_reqs[] = {
3483  &ia32_class_reg_req_gp,
3484  &ia32_class_reg_req_gp,
3485  &arch_memory_requirement,
3486  &ia32_class_reg_req_xmm,
3487  &ia32_class_reg_req_xmm,
3488  };
3489 
3490  /* construct in array */
3491  ir_node *const in[] = {
3492  base,
3493  index,
3494  mem,
3495  left,
3496  right,
3497  };
3498 
3499  ir_graph *const irg = get_irn_irg(block);
3500  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Orp, ia32_mode_float64, 5, in);
3501 
3502  /* flags */
3503  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3504  irn_flags |= arch_irn_flag_rematerializable;
3505 
3506  /* init node attributes */
3507  int const n_res = 3;
3508  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3509  (void)attr; /* avoid potential warning */
3510  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3511  set_ia32_am_support(res, ia32_am_binary);
3512  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3513  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
3514  out_infos[1].req = &ia32_class_reg_req_flags;
3515  out_infos[2].req = &arch_memory_requirement;
3516 
3517  verify_new_node(res);
3518  return optimize_node(res);
3519 }
3520 
3521 ir_node *new_bd_ia32_Outport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *value, ir_node *mem, x86_insn_size_t size)
3522 {
3523  static arch_register_req_t const *in_reqs[] = {
3524  &ia32_single_reg_req_gp_edx,
3525  &ia32_single_reg_req_gp_eax,
3526  &arch_memory_requirement,
3527  };
3528 
3529  /* construct in array */
3530  ir_node *const in[] = {
3531  port,
3532  value,
3533  mem,
3534  };
3535 
3536  ir_graph *const irg = get_irn_irg(block);
3537  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Outport, mode_M, 3, in);
3538 
3539  /* flags */
3540  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3541  irn_flags |= arch_irn_flag_rematerializable;
3542 
3543  /* init node attributes */
3544  int const n_res = 1;
3545  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3546  (void)attr; /* avoid potential warning */
3547  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3548  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3549  out_infos[0].req = &arch_memory_requirement;
3550 
3551  verify_new_node(res);
3552  return optimize_node(res);
3553 }
3554 
3555 ir_node *new_bd_ia32_Pop(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack, x86_insn_size_t size)
3556 {
3557  static arch_register_req_t const *in_reqs[] = {
3558  &arch_memory_requirement,
3559  &ia32_single_reg_req_gp_esp,
3560  };
3561 
3562  /* construct in array */
3563  ir_node *const in[] = {
3564  mem,
3565  stack,
3566  };
3567 
3568  ir_graph *const irg = get_irn_irg(block);
3569  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Pop, mode_T, 2, in);
3570 
3571  /* flags */
3572  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3573 
3574  /* init node attributes */
3575  int const n_res = 4;
3576  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3577  (void)attr; /* avoid potential warning */
3578  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3579  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3580  out_infos[0].req = &ia32_class_reg_req_gp;
3581  out_infos[1].req = &arch_no_requirement;
3582  out_infos[2].req = &arch_memory_requirement;
3583  out_infos[3].req = &ia32_requirements_gp_esp_I;
3584 
3585  verify_new_node(res);
3586  return optimize_node(res);
3587 }
3588 
3589 ir_node *new_bd_ia32_Pop_ebp(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack, x86_insn_size_t size)
3590 {
3591  static arch_register_req_t const *in_reqs[] = {
3592  &arch_memory_requirement,
3593  &ia32_single_reg_req_gp_esp,
3594  };
3595 
3596  /* construct in array */
3597  ir_node *const in[] = {
3598  mem,
3599  stack,
3600  };
3601 
3602  ir_graph *const irg = get_irn_irg(block);
3603  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Pop, mode_T, 2, in);
3604 
3605  /* flags */
3606  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3607 
3608  /* init node attributes */
3609  int const n_res = 4;
3610  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3611  (void)attr; /* avoid potential warning */
3612  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3613  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3614  out_infos[0].req = &ia32_requirements_gp_ebp_I;
3615  out_infos[1].req = &arch_no_requirement;
3616  out_infos[2].req = &arch_memory_requirement;
3617  out_infos[3].req = &ia32_requirements_gp_esp_I;
3618 
3619  verify_new_node(res);
3620  return optimize_node(res);
3621 }
3622 
3623 ir_node *new_bd_ia32_PopMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, x86_insn_size_t size)
3624 {
3625  static arch_register_req_t const *in_reqs[] = {
3626  &ia32_class_reg_req_gp,
3627  &ia32_class_reg_req_gp,
3628  &arch_memory_requirement,
3629  &ia32_single_reg_req_gp_esp,
3630  };
3631 
3632  /* construct in array */
3633  ir_node *const in[] = {
3634  base,
3635  index,
3636  mem,
3637  stack,
3638  };
3639 
3640  ir_graph *const irg = get_irn_irg(block);
3641  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PopMem, mode_T, 4, in);
3642 
3643  /* flags */
3644  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3645 
3646  /* init node attributes */
3647  int const n_res = 4;
3648  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3649  (void)attr; /* avoid potential warning */
3650  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3651  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3652  out_infos[0].req = &arch_no_requirement;
3653  out_infos[1].req = &arch_no_requirement;
3654  out_infos[2].req = &arch_memory_requirement;
3655  out_infos[3].req = &ia32_requirements_gp_esp_I;
3656 
3657  verify_new_node(res);
3658  return optimize_node(res);
3659 }
3660 
3661 ir_node *new_bd_ia32_Popcnt(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand, x86_insn_size_t size)
3662 {
3663  static arch_register_req_t const *in_reqs[] = {
3664  &ia32_class_reg_req_gp,
3665  &ia32_class_reg_req_gp,
3666  &arch_memory_requirement,
3667  &ia32_class_reg_req_gp,
3668  };
3669 
3670  /* construct in array */
3671  ir_node *const in[] = {
3672  base,
3673  index,
3674  mem,
3675  operand,
3676  };
3677 
3678  ir_graph *const irg = get_irn_irg(block);
3679  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Popcnt, ia32_mode_gp, 4, in);
3680 
3681  /* flags */
3682  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3683  irn_flags |= arch_irn_flag_modify_flags;
3684  irn_flags |= arch_irn_flag_rematerializable;
3685 
3686  /* init node attributes */
3687  int const n_res = 3;
3688  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3689  (void)attr; /* avoid potential warning */
3690  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3691  set_ia32_am_support(res, ia32_am_unary);
3692  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3693  out_infos[0].req = &ia32_class_reg_req_gp;
3694  out_infos[1].req = &ia32_class_reg_req_flags;
3695  out_infos[2].req = &arch_memory_requirement;
3696 
3697  verify_new_node(res);
3698  return optimize_node(res);
3699 }
3700 
3701 ir_node *new_bd_ia32_Prefetch(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3702 {
3703  static arch_register_req_t const *in_reqs[] = {
3704  &ia32_class_reg_req_gp,
3705  &ia32_class_reg_req_gp,
3706  &arch_memory_requirement,
3707  };
3708 
3709  /* construct in array */
3710  ir_node *const in[] = {
3711  base,
3712  index,
3713  mem,
3714  };
3715 
3716  ir_graph *const irg = get_irn_irg(block);
3717  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Prefetch, mode_M, 3, in);
3718 
3719  /* flags */
3720  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3721 
3722  /* init node attributes */
3723  int const n_res = 1;
3724  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3725  (void)attr; /* avoid potential warning */
3726  x86_insn_size_t const size = X86_SIZE_8;
3727  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3728  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3729  out_infos[0].req = &arch_memory_requirement;
3730 
3731  verify_new_node(res);
3732  return optimize_node(res);
3733 }
3734 
3735 ir_node *new_bd_ia32_PrefetchNTA(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3736 {
3737  static arch_register_req_t const *in_reqs[] = {
3738  &ia32_class_reg_req_gp,
3739  &ia32_class_reg_req_gp,
3740  &arch_memory_requirement,
3741  };
3742 
3743  /* construct in array */
3744  ir_node *const in[] = {
3745  base,
3746  index,
3747  mem,
3748  };
3749 
3750  ir_graph *const irg = get_irn_irg(block);
3751  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchNTA, mode_M, 3, in);
3752 
3753  /* flags */
3754  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3755 
3756  /* init node attributes */
3757  int const n_res = 1;
3758  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3759  (void)attr; /* avoid potential warning */
3760  x86_insn_size_t const size = X86_SIZE_8;
3761  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3762  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3763  out_infos[0].req = &arch_memory_requirement;
3764 
3765  verify_new_node(res);
3766  return optimize_node(res);
3767 }
3768 
3769 ir_node *new_bd_ia32_PrefetchT0(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3770 {
3771  static arch_register_req_t const *in_reqs[] = {
3772  &ia32_class_reg_req_gp,
3773  &ia32_class_reg_req_gp,
3774  &arch_memory_requirement,
3775  };
3776 
3777  /* construct in array */
3778  ir_node *const in[] = {
3779  base,
3780  index,
3781  mem,
3782  };
3783 
3784  ir_graph *const irg = get_irn_irg(block);
3785  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchT0, mode_M, 3, in);
3786 
3787  /* flags */
3788  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3789 
3790  /* init node attributes */
3791  int const n_res = 1;
3792  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3793  (void)attr; /* avoid potential warning */
3794  x86_insn_size_t const size = X86_SIZE_8;
3795  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3796  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3797  out_infos[0].req = &arch_memory_requirement;
3798 
3799  verify_new_node(res);
3800  return optimize_node(res);
3801 }
3802 
3803 ir_node *new_bd_ia32_PrefetchT1(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3804 {
3805  static arch_register_req_t const *in_reqs[] = {
3806  &ia32_class_reg_req_gp,
3807  &ia32_class_reg_req_gp,
3808  &arch_memory_requirement,
3809  };
3810 
3811  /* construct in array */
3812  ir_node *const in[] = {
3813  base,
3814  index,
3815  mem,
3816  };
3817 
3818  ir_graph *const irg = get_irn_irg(block);
3819  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchT1, mode_M, 3, in);
3820 
3821  /* flags */
3822  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3823 
3824  /* init node attributes */
3825  int const n_res = 1;
3826  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3827  (void)attr; /* avoid potential warning */
3828  x86_insn_size_t const size = X86_SIZE_8;
3829  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3830  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3831  out_infos[0].req = &arch_memory_requirement;
3832 
3833  verify_new_node(res);
3834  return optimize_node(res);
3835 }
3836 
3837 ir_node *new_bd_ia32_PrefetchT2(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3838 {
3839  static arch_register_req_t const *in_reqs[] = {
3840  &ia32_class_reg_req_gp,
3841  &ia32_class_reg_req_gp,
3842  &arch_memory_requirement,
3843  };
3844 
3845  /* construct in array */
3846  ir_node *const in[] = {
3847  base,
3848  index,
3849  mem,
3850  };
3851 
3852  ir_graph *const irg = get_irn_irg(block);
3853  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchT2, mode_M, 3, in);
3854 
3855  /* flags */
3856  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3857 
3858  /* init node attributes */
3859  int const n_res = 1;
3860  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3861  (void)attr; /* avoid potential warning */
3862  x86_insn_size_t const size = X86_SIZE_8;
3863  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3864  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3865  out_infos[0].req = &arch_memory_requirement;
3866 
3867  verify_new_node(res);
3868  return optimize_node(res);
3869 }
3870 
3871 ir_node *new_bd_ia32_PrefetchW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem)
3872 {
3873  static arch_register_req_t const *in_reqs[] = {
3874  &ia32_class_reg_req_gp,
3875  &ia32_class_reg_req_gp,
3876  &arch_memory_requirement,
3877  };
3878 
3879  /* construct in array */
3880  ir_node *const in[] = {
3881  base,
3882  index,
3883  mem,
3884  };
3885 
3886  ir_graph *const irg = get_irn_irg(block);
3887  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PrefetchW, mode_M, 3, in);
3888 
3889  /* flags */
3890  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3891 
3892  /* init node attributes */
3893  int const n_res = 1;
3894  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3895  (void)attr; /* avoid potential warning */
3896  x86_insn_size_t const size = X86_SIZE_8;
3897  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3898  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3899  out_infos[0].req = &arch_memory_requirement;
3900 
3901  verify_new_node(res);
3902  return optimize_node(res);
3903 }
3904 
3905 ir_node *new_bd_ia32_Pslld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size)
3906 {
3907  static arch_register_req_t const *in_reqs[] = {
3908  &ia32_class_reg_req_xmm,
3909  &ia32_class_reg_req_xmm,
3910  };
3911 
3912  /* construct in array */
3913  ir_node *const in[] = {
3914  op0,
3915  op1,
3916  };
3917 
3918  ir_graph *const irg = get_irn_irg(block);
3919  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Pslld, ia32_mode_float64, 2, in);
3920 
3921  /* flags */
3922  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3923  irn_flags |= arch_irn_flag_rematerializable;
3924 
3925  /* init node attributes */
3926  int const n_res = 1;
3927  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3928  (void)attr; /* avoid potential warning */
3929  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3930  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3931  out_infos[0].req = &ia32_requirements_xmm_in_r0_not_in_r1;
3932 
3933  verify_new_node(res);
3934  return optimize_node(res);
3935 }
3936 
3937 ir_node *new_bd_ia32_Psllq(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size)
3938 {
3939  static arch_register_req_t const *in_reqs[] = {
3940  &ia32_class_reg_req_xmm,
3941  &ia32_class_reg_req_xmm,
3942  };
3943 
3944  /* construct in array */
3945  ir_node *const in[] = {
3946  op0,
3947  op1,
3948  };
3949 
3950  ir_graph *const irg = get_irn_irg(block);
3951  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Psllq, ia32_mode_float64, 2, in);
3952 
3953  /* flags */
3954  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3955  irn_flags |= arch_irn_flag_rematerializable;
3956 
3957  /* init node attributes */
3958  int const n_res = 1;
3959  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3960  (void)attr; /* avoid potential warning */
3961  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3962  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3963  out_infos[0].req = &ia32_requirements_xmm_in_r0_not_in_r1;
3964 
3965  verify_new_node(res);
3966  return optimize_node(res);
3967 }
3968 
3969 ir_node *new_bd_ia32_Psrld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1, x86_insn_size_t size)
3970 {
3971  static arch_register_req_t const *in_reqs[] = {
3972  &ia32_class_reg_req_xmm,
3973  &ia32_class_reg_req_xmm,
3974  };
3975 
3976  /* construct in array */
3977  ir_node *const in[] = {
3978  op0,
3979  op1,
3980  };
3981 
3982  ir_graph *const irg = get_irn_irg(block);
3983  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Psrld, ia32_mode_float64, 2, in);
3984 
3985  /* flags */
3986  arch_irn_flags_t irn_flags = arch_irn_flags_none;
3987  irn_flags |= arch_irn_flag_rematerializable;
3988 
3989  /* init node attributes */
3990  int const n_res = 1;
3991  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
3992  (void)attr; /* avoid potential warning */
3993  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
3994  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
3995  out_infos[0].req = &ia32_requirements_xmm_in_r0_not_in_r1;
3996 
3997  verify_new_node(res);
3998  return optimize_node(res);
3999 }
4000 
4001 ir_node *new_bd_ia32_Push(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *stack, x86_insn_size_t size)
4002 {
4003  static arch_register_req_t const *in_reqs[] = {
4004  &ia32_class_reg_req_gp,
4005  &ia32_class_reg_req_gp,
4006  &arch_memory_requirement,
4007  &ia32_class_reg_req_gp,
4008  &ia32_single_reg_req_gp_esp,
4009  };
4010 
4011  /* construct in array */
4012  ir_node *const in[] = {
4013  base,
4014  index,
4015  mem,
4016  val,
4017  stack,
4018  };
4019 
4020  ir_graph *const irg = get_irn_irg(block);
4021  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Push, mode_T, 5, in);
4022 
4023  /* flags */
4024  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4025 
4026  /* init node attributes */
4027  int const n_res = 2;
4028  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4029  (void)attr; /* avoid potential warning */
4030  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4031  set_ia32_am_support(res, ia32_am_unary);
4032  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4033  out_infos[0].req = &arch_memory_requirement;
4034  out_infos[1].req = &ia32_requirements_gp_esp_I;
4035 
4036  verify_new_node(res);
4037  return optimize_node(res);
4038 }
4039 
4040 ir_node *new_bd_ia32_PushEax(dbg_info *dbgi, ir_node *block, ir_node *stack)
4041 {
4042  static arch_register_req_t const *in_reqs[] = {
4043  &ia32_single_reg_req_gp_esp,
4044  };
4045 
4046  /* construct in array */
4047  ir_node *const in[] = {
4048  stack,
4049  };
4050 
4051  ir_graph *const irg = get_irn_irg(block);
4052  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_PushEax, ia32_mode_gp, 1, in);
4053 
4054  /* flags */
4055  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4056 
4057  /* init node attributes */
4058  int const n_res = 1;
4059  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4060  (void)attr; /* avoid potential warning */
4061  x86_insn_size_t const size = X86_SIZE_32;
4062  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4063  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4064  out_infos[0].req = &ia32_requirements_gp_esp_I;
4065 
4066  verify_new_node(res);
4067  return optimize_node(res);
4068 }
4069 
4070 ir_node *new_bd_ia32_Return(dbg_info *dbgi, ir_node *block, int const arity, ir_node *const *const in, arch_register_req_t const **const in_reqs, uint16_t pop)
4071 {
4072 
4073 
4074  ir_graph *const irg = get_irn_irg(block);
4075  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Return, mode_X, arity, in);
4076 
4077  /* flags */
4078  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4079 
4080  /* init node attributes */
4081  int const n_res = 1;
4082  ia32_return_attr_t *const attr = (ia32_return_attr_t*)get_irn_generic_attr(res);
4083  (void)attr; /* avoid potential warning */
4084  x86_insn_size_t const size = X86_SIZE_32;
4085  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4086  init_ia32_return_attributes(res, pop);
4087  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4088  out_infos[0].req = &arch_exec_requirement;
4089 
4090  verify_new_node(res);
4091  return optimize_node(res);
4092 }
4093 
4094 ir_node *new_bd_ia32_Rol(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4095 {
4096  static arch_register_req_t const *in_reqs[] = {
4097  &ia32_class_reg_req_gp,
4098  &ia32_single_reg_req_gp_ecx,
4099  };
4100 
4101  /* construct in array */
4102  ir_node *const in[] = {
4103  val,
4104  count,
4105  };
4106 
4107  ir_graph *const irg = get_irn_irg(block);
4108  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Rol, ia32_mode_gp, 2, in);
4109 
4110  /* flags */
4111  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4112  irn_flags |= arch_irn_flag_modify_flags;
4113  irn_flags |= arch_irn_flag_rematerializable;
4114 
4115  /* init node attributes */
4116  int const n_res = 2;
4117  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4118  (void)attr; /* avoid potential warning */
4119  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4120  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4121  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4122  out_infos[1].req = &ia32_class_reg_req_flags;
4123 
4124  verify_new_node(res);
4125  return optimize_node(res);
4126 }
4127 
4128 ir_node *new_bd_ia32_Rol_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4129 {
4130  static arch_register_req_t const *in_reqs[] = {
4131  &ia32_requirements_gp_eax_ebx_ecx_edx,
4132  &ia32_single_reg_req_gp_ecx,
4133  };
4134 
4135  /* construct in array */
4136  ir_node *const in[] = {
4137  val,
4138  count,
4139  };
4140 
4141  ir_graph *const irg = get_irn_irg(block);
4142  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Rol, ia32_mode_gp, 2, in);
4143 
4144  /* flags */
4145  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4146  irn_flags |= arch_irn_flag_modify_flags;
4147  irn_flags |= arch_irn_flag_rematerializable;
4148 
4149  /* init node attributes */
4150  int const n_res = 2;
4151  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4152  (void)attr; /* avoid potential warning */
4153  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4154  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4155  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4156  out_infos[1].req = &ia32_class_reg_req_flags;
4157 
4158  verify_new_node(res);
4159  return optimize_node(res);
4160 }
4161 
4162 ir_node *new_bd_ia32_RolMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4163 {
4164  static arch_register_req_t const *in_reqs[] = {
4165  &ia32_class_reg_req_gp,
4166  &ia32_class_reg_req_gp,
4167  &arch_memory_requirement,
4168  &ia32_single_reg_req_gp_ecx,
4169  };
4170 
4171  /* construct in array */
4172  ir_node *const in[] = {
4173  base,
4174  index,
4175  mem,
4176  count,
4177  };
4178 
4179  ir_graph *const irg = get_irn_irg(block);
4180  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_RolMem, mode_T, 4, in);
4181 
4182  /* flags */
4183  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4184  irn_flags |= arch_irn_flag_modify_flags;
4185  irn_flags |= arch_irn_flag_rematerializable;
4186 
4187  /* init node attributes */
4188  int const n_res = 3;
4189  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4190  (void)attr; /* avoid potential warning */
4191  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4192  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4193  out_infos[0].req = &arch_no_requirement;
4194  out_infos[1].req = &ia32_class_reg_req_flags;
4195  out_infos[2].req = &arch_memory_requirement;
4196 
4197  verify_new_node(res);
4198  return optimize_node(res);
4199 }
4200 
4201 ir_node *new_bd_ia32_Ror(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4202 {
4203  static arch_register_req_t const *in_reqs[] = {
4204  &ia32_class_reg_req_gp,
4205  &ia32_single_reg_req_gp_ecx,
4206  };
4207 
4208  /* construct in array */
4209  ir_node *const in[] = {
4210  val,
4211  count,
4212  };
4213 
4214  ir_graph *const irg = get_irn_irg(block);
4215  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Ror, ia32_mode_gp, 2, in);
4216 
4217  /* flags */
4218  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4219  irn_flags |= arch_irn_flag_modify_flags;
4220  irn_flags |= arch_irn_flag_rematerializable;
4221 
4222  /* init node attributes */
4223  int const n_res = 2;
4224  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4225  (void)attr; /* avoid potential warning */
4226  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4227  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4228  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4229  out_infos[1].req = &ia32_class_reg_req_flags;
4230 
4231  verify_new_node(res);
4232  return optimize_node(res);
4233 }
4234 
4235 ir_node *new_bd_ia32_Ror_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4236 {
4237  static arch_register_req_t const *in_reqs[] = {
4238  &ia32_requirements_gp_eax_ebx_ecx_edx,
4239  &ia32_single_reg_req_gp_ecx,
4240  };
4241 
4242  /* construct in array */
4243  ir_node *const in[] = {
4244  val,
4245  count,
4246  };
4247 
4248  ir_graph *const irg = get_irn_irg(block);
4249  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Ror, ia32_mode_gp, 2, in);
4250 
4251  /* flags */
4252  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4253  irn_flags |= arch_irn_flag_modify_flags;
4254  irn_flags |= arch_irn_flag_rematerializable;
4255 
4256  /* init node attributes */
4257  int const n_res = 2;
4258  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4259  (void)attr; /* avoid potential warning */
4260  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4261  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4262  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4263  out_infos[1].req = &ia32_class_reg_req_flags;
4264 
4265  verify_new_node(res);
4266  return optimize_node(res);
4267 }
4268 
4269 ir_node *new_bd_ia32_RorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4270 {
4271  static arch_register_req_t const *in_reqs[] = {
4272  &ia32_class_reg_req_gp,
4273  &ia32_class_reg_req_gp,
4274  &arch_memory_requirement,
4275  &ia32_single_reg_req_gp_ecx,
4276  };
4277 
4278  /* construct in array */
4279  ir_node *const in[] = {
4280  base,
4281  index,
4282  mem,
4283  count,
4284  };
4285 
4286  ir_graph *const irg = get_irn_irg(block);
4287  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_RorMem, mode_T, 4, in);
4288 
4289  /* flags */
4290  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4291  irn_flags |= arch_irn_flag_modify_flags;
4292  irn_flags |= arch_irn_flag_rematerializable;
4293 
4294  /* init node attributes */
4295  int const n_res = 3;
4296  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4297  (void)attr; /* avoid potential warning */
4298  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4299  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4300  out_infos[0].req = &arch_no_requirement;
4301  out_infos[1].req = &ia32_class_reg_req_flags;
4302  out_infos[2].req = &arch_memory_requirement;
4303 
4304  verify_new_node(res);
4305  return optimize_node(res);
4306 }
4307 
4308 ir_node *new_bd_ia32_Sahf(dbg_info *dbgi, ir_node *block, ir_node *val)
4309 {
4310  static arch_register_req_t const *in_reqs[] = {
4311  &ia32_single_reg_req_gp_eax,
4312  };
4313 
4314  /* construct in array */
4315  ir_node *const in[] = {
4316  val,
4317  };
4318 
4319  ir_graph *const irg = get_irn_irg(block);
4320  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sahf, ia32_mode_flags, 1, in);
4321 
4322  /* flags */
4323  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4324  irn_flags |= arch_irn_flag_rematerializable;
4325 
4326  /* init node attributes */
4327  int const n_res = 1;
4328  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4329  (void)attr; /* avoid potential warning */
4330  x86_insn_size_t const size = X86_SIZE_16;
4331  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4332  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4333  out_infos[0].req = &ia32_single_reg_req_flags_eflags;
4334 
4335  verify_new_node(res);
4336  return optimize_node(res);
4337 }
4338 
4339 ir_node *new_bd_ia32_Sar(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4340 {
4341  static arch_register_req_t const *in_reqs[] = {
4342  &ia32_class_reg_req_gp,
4343  &ia32_single_reg_req_gp_ecx,
4344  };
4345 
4346  /* construct in array */
4347  ir_node *const in[] = {
4348  val,
4349  count,
4350  };
4351 
4352  ir_graph *const irg = get_irn_irg(block);
4353  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sar, ia32_mode_gp, 2, in);
4354 
4355  /* flags */
4356  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4357  irn_flags |= arch_irn_flag_modify_flags;
4358  irn_flags |= arch_irn_flag_rematerializable;
4359 
4360  /* init node attributes */
4361  int const n_res = 2;
4362  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4363  (void)attr; /* avoid potential warning */
4364  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4365  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4366  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4367  out_infos[1].req = &ia32_class_reg_req_flags;
4368 
4369  verify_new_node(res);
4370  return optimize_node(res);
4371 }
4372 
4373 ir_node *new_bd_ia32_Sar_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4374 {
4375  static arch_register_req_t const *in_reqs[] = {
4376  &ia32_requirements_gp_eax_ebx_ecx_edx,
4377  &ia32_single_reg_req_gp_ecx,
4378  };
4379 
4380  /* construct in array */
4381  ir_node *const in[] = {
4382  val,
4383  count,
4384  };
4385 
4386  ir_graph *const irg = get_irn_irg(block);
4387  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sar, ia32_mode_gp, 2, in);
4388 
4389  /* flags */
4390  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4391  irn_flags |= arch_irn_flag_modify_flags;
4392  irn_flags |= arch_irn_flag_rematerializable;
4393 
4394  /* init node attributes */
4395  int const n_res = 2;
4396  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4397  (void)attr; /* avoid potential warning */
4398  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4399  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4400  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4401  out_infos[1].req = &ia32_class_reg_req_flags;
4402 
4403  verify_new_node(res);
4404  return optimize_node(res);
4405 }
4406 
4407 ir_node *new_bd_ia32_SarMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4408 {
4409  static arch_register_req_t const *in_reqs[] = {
4410  &ia32_class_reg_req_gp,
4411  &ia32_class_reg_req_gp,
4412  &arch_memory_requirement,
4413  &ia32_single_reg_req_gp_ecx,
4414  };
4415 
4416  /* construct in array */
4417  ir_node *const in[] = {
4418  base,
4419  index,
4420  mem,
4421  count,
4422  };
4423 
4424  ir_graph *const irg = get_irn_irg(block);
4425  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SarMem, mode_T, 4, in);
4426 
4427  /* flags */
4428  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4429  irn_flags |= arch_irn_flag_modify_flags;
4430  irn_flags |= arch_irn_flag_rematerializable;
4431 
4432  /* init node attributes */
4433  int const n_res = 3;
4434  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4435  (void)attr; /* avoid potential warning */
4436  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4437  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4438  out_infos[0].req = &arch_no_requirement;
4439  out_infos[1].req = &ia32_class_reg_req_flags;
4440  out_infos[2].req = &arch_memory_requirement;
4441 
4442  verify_new_node(res);
4443  return optimize_node(res);
4444 }
4445 
4446 ir_node *new_bd_ia32_Sbb(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, x86_insn_size_t size)
4447 {
4448  static arch_register_req_t const *in_reqs[] = {
4449  &ia32_class_reg_req_gp,
4450  &ia32_class_reg_req_gp,
4451  &arch_memory_requirement,
4452  &ia32_class_reg_req_gp,
4453  &ia32_class_reg_req_gp,
4454  &ia32_class_reg_req_flags,
4455  };
4456 
4457  /* construct in array */
4458  ir_node *const in[] = {
4459  base,
4460  index,
4461  mem,
4462  minuend,
4463  subtrahend,
4464  eflags,
4465  };
4466 
4467  ir_graph *const irg = get_irn_irg(block);
4468  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sbb, ia32_mode_gp, 6, in);
4469 
4470  /* flags */
4471  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4472  irn_flags |= arch_irn_flag_modify_flags;
4473 
4474  /* init node attributes */
4475  int const n_res = 3;
4476  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
4477  (void)attr; /* avoid potential warning */
4478  x86_condition_code_t condition_code = x86_cc_carry;
4479  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4480  init_ia32_condcode_attributes(res, condition_code);
4481  set_ia32_am_support(res, ia32_am_binary);
4482  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4483  out_infos[0].req = &ia32_requirements_gp_in_r3;
4484  out_infos[1].req = &ia32_class_reg_req_flags;
4485  out_infos[2].req = &arch_memory_requirement;
4486 
4487  verify_new_node(res);
4488  return optimize_node(res);
4489 }
4490 
4491 ir_node *new_bd_ia32_Sbb0(dbg_info *dbgi, ir_node *block, ir_node *op0, x86_insn_size_t size)
4492 {
4493  static arch_register_req_t const *in_reqs[] = {
4494  &ia32_class_reg_req_flags,
4495  };
4496 
4497  /* construct in array */
4498  ir_node *const in[] = {
4499  op0,
4500  };
4501 
4502  ir_graph *const irg = get_irn_irg(block);
4503  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sbb0, ia32_mode_gp, 1, in);
4504 
4505  /* flags */
4506  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4507  irn_flags |= arch_irn_flag_modify_flags;
4508 
4509  /* init node attributes */
4510  int const n_res = 2;
4511  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
4512  (void)attr; /* avoid potential warning */
4513  x86_condition_code_t condition_code = x86_cc_carry;
4514  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4515  init_ia32_condcode_attributes(res, condition_code);
4516  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4517  out_infos[0].req = &ia32_class_reg_req_gp;
4518  out_infos[1].req = &ia32_class_reg_req_flags;
4519 
4520  verify_new_node(res);
4521  return optimize_node(res);
4522 }
4523 
4524 ir_node *new_bd_ia32_Setcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, x86_condition_code_t condition_code)
4525 {
4526  static arch_register_req_t const *in_reqs[] = {
4527  &ia32_single_reg_req_flags_eflags,
4528  };
4529 
4530  /* construct in array */
4531  ir_node *const in[] = {
4532  eflags,
4533  };
4534 
4535  ir_graph *const irg = get_irn_irg(block);
4536  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Setcc, ia32_mode_gp, 1, in);
4537 
4538  /* flags */
4539  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4540 
4541  /* init node attributes */
4542  int const n_res = 1;
4543  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
4544  (void)attr; /* avoid potential warning */
4545  x86_insn_size_t const size = X86_SIZE_8;
4546  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4547  init_ia32_condcode_attributes(res, condition_code);
4548  if (condition_code & x86_cc_additional_float_cases) {
4549  arch_add_irn_flags(res, arch_irn_flag_modify_flags);
4550  /* attr->latency = 3; */
4551  }
4552 
4553  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4554  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx;
4555 
4556  verify_new_node(res);
4557  return optimize_node(res);
4558 }
4559 
4560 ir_node *new_bd_ia32_SetccMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *eflags, x86_condition_code_t condition_code)
4561 {
4562  static arch_register_req_t const *in_reqs[] = {
4563  &ia32_class_reg_req_gp,
4564  &ia32_class_reg_req_gp,
4565  &arch_memory_requirement,
4566  &ia32_single_reg_req_flags_eflags,
4567  };
4568 
4569  /* construct in array */
4570  ir_node *const in[] = {
4571  base,
4572  index,
4573  mem,
4574  eflags,
4575  };
4576 
4577  ir_graph *const irg = get_irn_irg(block);
4578  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SetccMem, mode_M, 4, in);
4579 
4580  /* flags */
4581  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4582 
4583  /* init node attributes */
4584  int const n_res = 1;
4585  ia32_condcode_attr_t *const attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res);
4586  (void)attr; /* avoid potential warning */
4587  x86_insn_size_t const size = X86_SIZE_8;
4588  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4589  init_ia32_condcode_attributes(res, condition_code);
4590  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4591  out_infos[0].req = &arch_memory_requirement;
4592 
4593  verify_new_node(res);
4594  return optimize_node(res);
4595 }
4596 
4597 ir_node *new_bd_ia32_Shl(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4598 {
4599  static arch_register_req_t const *in_reqs[] = {
4600  &ia32_class_reg_req_gp,
4601  &ia32_single_reg_req_gp_ecx,
4602  };
4603 
4604  /* construct in array */
4605  ir_node *const in[] = {
4606  val,
4607  count,
4608  };
4609 
4610  ir_graph *const irg = get_irn_irg(block);
4611  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Shl, ia32_mode_gp, 2, in);
4612 
4613  /* flags */
4614  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4615  irn_flags |= arch_irn_flag_modify_flags;
4616  irn_flags |= arch_irn_flag_rematerializable;
4617 
4618  /* init node attributes */
4619  int const n_res = 2;
4620  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4621  (void)attr; /* avoid potential warning */
4622  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4623  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4624  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4625  out_infos[1].req = &ia32_class_reg_req_flags;
4626 
4627  verify_new_node(res);
4628  return optimize_node(res);
4629 }
4630 
4631 ir_node *new_bd_ia32_Shl_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4632 {
4633  static arch_register_req_t const *in_reqs[] = {
4634  &ia32_requirements_gp_eax_ebx_ecx_edx,
4635  &ia32_single_reg_req_gp_ecx,
4636  };
4637 
4638  /* construct in array */
4639  ir_node *const in[] = {
4640  val,
4641  count,
4642  };
4643 
4644  ir_graph *const irg = get_irn_irg(block);
4645  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Shl, ia32_mode_gp, 2, in);
4646 
4647  /* flags */
4648  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4649  irn_flags |= arch_irn_flag_modify_flags;
4650  irn_flags |= arch_irn_flag_rematerializable;
4651 
4652  /* init node attributes */
4653  int const n_res = 2;
4654  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4655  (void)attr; /* avoid potential warning */
4656  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4657  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4658  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4659  out_infos[1].req = &ia32_class_reg_req_flags;
4660 
4661  verify_new_node(res);
4662  return optimize_node(res);
4663 }
4664 
4665 ir_node *new_bd_ia32_ShlD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count)
4666 {
4667  static arch_register_req_t const *in_reqs[] = {
4668  &ia32_class_reg_req_gp,
4669  &ia32_class_reg_req_gp,
4670  &ia32_single_reg_req_gp_ecx,
4671  };
4672 
4673  /* construct in array */
4674  ir_node *const in[] = {
4675  val_high,
4676  val_low,
4677  count,
4678  };
4679 
4680  ir_graph *const irg = get_irn_irg(block);
4681  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShlD, ia32_mode_gp, 3, in);
4682 
4683  /* flags */
4684  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4685  irn_flags |= arch_irn_flag_modify_flags;
4686  irn_flags |= arch_irn_flag_rematerializable;
4687 
4688  /* init node attributes */
4689  int const n_res = 2;
4690  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4691  (void)attr; /* avoid potential warning */
4692  x86_insn_size_t const size = X86_SIZE_32;
4693  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4694  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4695  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1_not_in_r2;
4696  out_infos[1].req = &ia32_class_reg_req_flags;
4697 
4698  verify_new_node(res);
4699  return optimize_node(res);
4700 }
4701 
4702 ir_node *new_bd_ia32_ShlD_imm(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count)
4703 {
4704  static arch_register_req_t const *in_reqs[] = {
4705  &ia32_class_reg_req_gp,
4706  &ia32_class_reg_req_gp,
4707  &ia32_single_reg_req_gp_ecx,
4708  };
4709 
4710  /* construct in array */
4711  ir_node *const in[] = {
4712  val_high,
4713  val_low,
4714  count,
4715  };
4716 
4717  ir_graph *const irg = get_irn_irg(block);
4718  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShlD, ia32_mode_gp, 3, in);
4719 
4720  /* flags */
4721  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4722  irn_flags |= arch_irn_flag_modify_flags;
4723  irn_flags |= arch_irn_flag_rematerializable;
4724 
4725  /* init node attributes */
4726  int const n_res = 2;
4727  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4728  (void)attr; /* avoid potential warning */
4729  x86_insn_size_t const size = X86_SIZE_32;
4730  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4731  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4732  out_infos[0].req = &ia32_requirements_gp_in_r0_in_r1;
4733  out_infos[1].req = &ia32_class_reg_req_flags;
4734 
4735  verify_new_node(res);
4736  return optimize_node(res);
4737 }
4738 
4739 ir_node *new_bd_ia32_ShlMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4740 {
4741  static arch_register_req_t const *in_reqs[] = {
4742  &ia32_class_reg_req_gp,
4743  &ia32_class_reg_req_gp,
4744  &arch_memory_requirement,
4745  &ia32_single_reg_req_gp_ecx,
4746  };
4747 
4748  /* construct in array */
4749  ir_node *const in[] = {
4750  base,
4751  index,
4752  mem,
4753  count,
4754  };
4755 
4756  ir_graph *const irg = get_irn_irg(block);
4757  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShlMem, mode_T, 4, in);
4758 
4759  /* flags */
4760  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4761  irn_flags |= arch_irn_flag_modify_flags;
4762  irn_flags |= arch_irn_flag_rematerializable;
4763 
4764  /* init node attributes */
4765  int const n_res = 3;
4766  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4767  (void)attr; /* avoid potential warning */
4768  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4769  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4770  out_infos[0].req = &arch_no_requirement;
4771  out_infos[1].req = &ia32_class_reg_req_flags;
4772  out_infos[2].req = &arch_memory_requirement;
4773 
4774  verify_new_node(res);
4775  return optimize_node(res);
4776 }
4777 
4778 ir_node *new_bd_ia32_Shr(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4779 {
4780  static arch_register_req_t const *in_reqs[] = {
4781  &ia32_class_reg_req_gp,
4782  &ia32_single_reg_req_gp_ecx,
4783  };
4784 
4785  /* construct in array */
4786  ir_node *const in[] = {
4787  val,
4788  count,
4789  };
4790 
4791  ir_graph *const irg = get_irn_irg(block);
4792  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Shr, ia32_mode_gp, 2, in);
4793 
4794  /* flags */
4795  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4796  irn_flags |= arch_irn_flag_modify_flags;
4797  irn_flags |= arch_irn_flag_rematerializable;
4798 
4799  /* init node attributes */
4800  int const n_res = 2;
4801  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4802  (void)attr; /* avoid potential warning */
4803  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4804  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4805  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4806  out_infos[1].req = &ia32_class_reg_req_flags;
4807 
4808  verify_new_node(res);
4809  return optimize_node(res);
4810 }
4811 
4812 ir_node *new_bd_ia32_Shr_8bit(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count, x86_insn_size_t size)
4813 {
4814  static arch_register_req_t const *in_reqs[] = {
4815  &ia32_requirements_gp_eax_ebx_ecx_edx,
4816  &ia32_single_reg_req_gp_ecx,
4817  };
4818 
4819  /* construct in array */
4820  ir_node *const in[] = {
4821  val,
4822  count,
4823  };
4824 
4825  ir_graph *const irg = get_irn_irg(block);
4826  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Shr, ia32_mode_gp, 2, in);
4827 
4828  /* flags */
4829  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4830  irn_flags |= arch_irn_flag_modify_flags;
4831  irn_flags |= arch_irn_flag_rematerializable;
4832 
4833  /* init node attributes */
4834  int const n_res = 2;
4835  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4836  (void)attr; /* avoid potential warning */
4837  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4838  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4839  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1;
4840  out_infos[1].req = &ia32_class_reg_req_flags;
4841 
4842  verify_new_node(res);
4843  return optimize_node(res);
4844 }
4845 
4846 ir_node *new_bd_ia32_ShrD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count)
4847 {
4848  static arch_register_req_t const *in_reqs[] = {
4849  &ia32_class_reg_req_gp,
4850  &ia32_class_reg_req_gp,
4851  &ia32_single_reg_req_gp_ecx,
4852  };
4853 
4854  /* construct in array */
4855  ir_node *const in[] = {
4856  val_high,
4857  val_low,
4858  count,
4859  };
4860 
4861  ir_graph *const irg = get_irn_irg(block);
4862  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShrD, ia32_mode_gp, 3, in);
4863 
4864  /* flags */
4865  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4866  irn_flags |= arch_irn_flag_modify_flags;
4867  irn_flags |= arch_irn_flag_rematerializable;
4868 
4869  /* init node attributes */
4870  int const n_res = 2;
4871  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4872  (void)attr; /* avoid potential warning */
4873  x86_insn_size_t const size = X86_SIZE_32;
4874  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4875  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4876  out_infos[0].req = &ia32_requirements_gp_in_r0_not_in_r1_not_in_r2;
4877  out_infos[1].req = &ia32_class_reg_req_flags;
4878 
4879  verify_new_node(res);
4880  return optimize_node(res);
4881 }
4882 
4883 ir_node *new_bd_ia32_ShrD_imm(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count)
4884 {
4885  static arch_register_req_t const *in_reqs[] = {
4886  &ia32_class_reg_req_gp,
4887  &ia32_class_reg_req_gp,
4888  &ia32_single_reg_req_gp_ecx,
4889  };
4890 
4891  /* construct in array */
4892  ir_node *const in[] = {
4893  val_high,
4894  val_low,
4895  count,
4896  };
4897 
4898  ir_graph *const irg = get_irn_irg(block);
4899  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShrD, ia32_mode_gp, 3, in);
4900 
4901  /* flags */
4902  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4903  irn_flags |= arch_irn_flag_modify_flags;
4904  irn_flags |= arch_irn_flag_rematerializable;
4905 
4906  /* init node attributes */
4907  int const n_res = 2;
4908  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4909  (void)attr; /* avoid potential warning */
4910  x86_insn_size_t const size = X86_SIZE_32;
4911  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4912  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4913  out_infos[0].req = &ia32_requirements_gp_in_r0_in_r1;
4914  out_infos[1].req = &ia32_class_reg_req_flags;
4915 
4916  verify_new_node(res);
4917  return optimize_node(res);
4918 }
4919 
4920 ir_node *new_bd_ia32_ShrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count, x86_insn_size_t size)
4921 {
4922  static arch_register_req_t const *in_reqs[] = {
4923  &ia32_class_reg_req_gp,
4924  &ia32_class_reg_req_gp,
4925  &arch_memory_requirement,
4926  &ia32_single_reg_req_gp_ecx,
4927  };
4928 
4929  /* construct in array */
4930  ir_node *const in[] = {
4931  base,
4932  index,
4933  mem,
4934  count,
4935  };
4936 
4937  ir_graph *const irg = get_irn_irg(block);
4938  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ShrMem, mode_T, 4, in);
4939 
4940  /* flags */
4941  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4942  irn_flags |= arch_irn_flag_modify_flags;
4943  irn_flags |= arch_irn_flag_rematerializable;
4944 
4945  /* init node attributes */
4946  int const n_res = 3;
4947  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4948  (void)attr; /* avoid potential warning */
4949  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4950  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4951  out_infos[0].req = &arch_no_requirement;
4952  out_infos[1].req = &ia32_class_reg_req_flags;
4953  out_infos[2].req = &arch_memory_requirement;
4954 
4955  verify_new_node(res);
4956  return optimize_node(res);
4957 }
4958 
4959 ir_node *new_bd_ia32_Stc(dbg_info *dbgi, ir_node *block)
4960 {
4961  arch_register_req_t const **const in_reqs = NULL;
4962 
4963 
4964  ir_graph *const irg = get_irn_irg(block);
4965  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Stc, ia32_mode_flags, 0, NULL);
4966 
4967  /* flags */
4968  arch_irn_flags_t irn_flags = arch_irn_flags_none;
4969  irn_flags |= arch_irn_flag_modify_flags;
4970  irn_flags |= arch_irn_flag_rematerializable;
4971 
4972  /* init node attributes */
4973  int const n_res = 1;
4974  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
4975  (void)attr; /* avoid potential warning */
4976  x86_insn_size_t const size = X86_SIZE_32;
4977  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
4978  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
4979  out_infos[0].req = &ia32_class_reg_req_flags;
4980 
4981  verify_new_node(res);
4982  return optimize_node(res);
4983 }
4984 
4985 ir_node *new_bd_ia32_Store(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
4986 {
4987  static arch_register_req_t const *in_reqs[] = {
4988  &ia32_class_reg_req_gp,
4989  &ia32_class_reg_req_gp,
4990  &arch_memory_requirement,
4991  &ia32_class_reg_req_gp,
4992  };
4993 
4994  /* construct in array */
4995  ir_node *const in[] = {
4996  base,
4997  index,
4998  mem,
4999  val,
5000  };
5001 
5002  ir_graph *const irg = get_irn_irg(block);
5003  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Store, mode_T, 4, in);
5004 
5005  /* flags */
5006  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5007 
5008  /* init node attributes */
5009  int const n_res = 3;
5010  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5011  (void)attr; /* avoid potential warning */
5012  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5013  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5014  out_infos[0].req = &arch_memory_requirement;
5015  out_infos[1].req = &arch_exec_requirement;
5016  out_infos[2].req = &arch_exec_requirement;
5017 
5018  verify_new_node(res);
5019  return optimize_node(res);
5020 }
5021 
5022 ir_node *new_bd_ia32_Store_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5023 {
5024  static arch_register_req_t const *in_reqs[] = {
5025  &ia32_class_reg_req_gp,
5026  &ia32_class_reg_req_gp,
5027  &arch_memory_requirement,
5028  &ia32_requirements_gp_eax_ebx_ecx_edx,
5029  };
5030 
5031  /* construct in array */
5032  ir_node *const in[] = {
5033  base,
5034  index,
5035  mem,
5036  val,
5037  };
5038 
5039  ir_graph *const irg = get_irn_irg(block);
5040  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Store, mode_T, 4, in);
5041 
5042  /* flags */
5043  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5044 
5045  /* init node attributes */
5046  int const n_res = 3;
5047  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5048  (void)attr; /* avoid potential warning */
5049  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5050  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5051  out_infos[0].req = &arch_memory_requirement;
5052  out_infos[1].req = &arch_exec_requirement;
5053  out_infos[2].req = &arch_exec_requirement;
5054 
5055  verify_new_node(res);
5056  return optimize_node(res);
5057 }
5058 
5059 ir_node *new_bd_ia32_Sub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size)
5060 {
5061  static arch_register_req_t const *in_reqs[] = {
5062  &ia32_class_reg_req_gp,
5063  &ia32_class_reg_req_gp,
5064  &arch_memory_requirement,
5065  &ia32_class_reg_req_gp,
5066  &ia32_class_reg_req_gp,
5067  };
5068 
5069  /* construct in array */
5070  ir_node *const in[] = {
5071  base,
5072  index,
5073  mem,
5074  minuend,
5075  subtrahend,
5076  };
5077 
5078  ir_graph *const irg = get_irn_irg(block);
5079  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sub, ia32_mode_gp, 5, in);
5080 
5081  /* flags */
5082  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5083  irn_flags |= arch_irn_flag_modify_flags;
5084  irn_flags |= arch_irn_flag_rematerializable;
5085 
5086  /* init node attributes */
5087  int const n_res = 3;
5088  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5089  (void)attr; /* avoid potential warning */
5090  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5091  set_ia32_am_support(res, ia32_am_binary);
5092  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5093  out_infos[0].req = &ia32_requirements_gp_in_r3;
5094  out_infos[1].req = &ia32_class_reg_req_flags;
5095  out_infos[2].req = &arch_memory_requirement;
5096 
5097  verify_new_node(res);
5098  return optimize_node(res);
5099 }
5100 
5101 ir_node *new_bd_ia32_Sub_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size)
5102 {
5103  static arch_register_req_t const *in_reqs[] = {
5104  &ia32_class_reg_req_gp,
5105  &ia32_class_reg_req_gp,
5106  &arch_memory_requirement,
5107  &ia32_requirements_gp_eax_ebx_ecx_edx,
5108  &ia32_requirements_gp_eax_ebx_ecx_edx,
5109  };
5110 
5111  /* construct in array */
5112  ir_node *const in[] = {
5113  base,
5114  index,
5115  mem,
5116  minuend,
5117  subtrahend,
5118  };
5119 
5120  ir_graph *const irg = get_irn_irg(block);
5121  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Sub, ia32_mode_gp, 5, in);
5122 
5123  /* flags */
5124  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5125  irn_flags |= arch_irn_flag_modify_flags;
5126  irn_flags |= arch_irn_flag_rematerializable;
5127 
5128  /* init node attributes */
5129  int const n_res = 3;
5130  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5131  (void)attr; /* avoid potential warning */
5132  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5133  set_ia32_am_support(res, ia32_am_binary);
5134  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5135  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3;
5136  out_infos[1].req = &ia32_class_reg_req_flags;
5137  out_infos[2].req = &arch_memory_requirement;
5138 
5139  verify_new_node(res);
5140  return optimize_node(res);
5141 }
5142 
5143 ir_node *new_bd_ia32_SubMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5144 {
5145  static arch_register_req_t const *in_reqs[] = {
5146  &ia32_class_reg_req_gp,
5147  &ia32_class_reg_req_gp,
5148  &arch_memory_requirement,
5149  &ia32_class_reg_req_gp,
5150  };
5151 
5152  /* construct in array */
5153  ir_node *const in[] = {
5154  base,
5155  index,
5156  mem,
5157  val,
5158  };
5159 
5160  ir_graph *const irg = get_irn_irg(block);
5161  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SubMem, mode_T, 4, in);
5162 
5163  /* flags */
5164  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5165  irn_flags |= arch_irn_flag_modify_flags;
5166  irn_flags |= arch_irn_flag_rematerializable;
5167 
5168  /* init node attributes */
5169  int const n_res = 3;
5170  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5171  (void)attr; /* avoid potential warning */
5172  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5173  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5174  out_infos[0].req = &arch_no_requirement;
5175  out_infos[1].req = &ia32_class_reg_req_flags;
5176  out_infos[2].req = &arch_memory_requirement;
5177 
5178  verify_new_node(res);
5179  return optimize_node(res);
5180 }
5181 
5182 ir_node *new_bd_ia32_SubMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5183 {
5184  static arch_register_req_t const *in_reqs[] = {
5185  &ia32_class_reg_req_gp,
5186  &ia32_class_reg_req_gp,
5187  &arch_memory_requirement,
5188  &ia32_requirements_gp_eax_ebx_ecx_edx,
5189  };
5190 
5191  /* construct in array */
5192  ir_node *const in[] = {
5193  base,
5194  index,
5195  mem,
5196  val,
5197  };
5198 
5199  ir_graph *const irg = get_irn_irg(block);
5200  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SubMem, mode_T, 4, in);
5201 
5202  /* flags */
5203  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5204  irn_flags |= arch_irn_flag_modify_flags;
5205  irn_flags |= arch_irn_flag_rematerializable;
5206 
5207  /* init node attributes */
5208  int const n_res = 3;
5209  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5210  (void)attr; /* avoid potential warning */
5211  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5212  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5213  out_infos[0].req = &arch_no_requirement;
5214  out_infos[1].req = &ia32_class_reg_req_flags;
5215  out_infos[2].req = &arch_memory_requirement;
5216 
5217  verify_new_node(res);
5218  return optimize_node(res);
5219 }
5220 
5221 ir_node *new_bd_ia32_SubSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *amount)
5222 {
5223  static arch_register_req_t const *in_reqs[] = {
5224  &ia32_class_reg_req_gp,
5225  &ia32_class_reg_req_gp,
5226  &arch_memory_requirement,
5227  &ia32_single_reg_req_gp_esp,
5228  &ia32_class_reg_req_gp,
5229  };
5230 
5231  /* construct in array */
5232  ir_node *const in[] = {
5233  base,
5234  index,
5235  mem,
5236  stack,
5237  amount,
5238  };
5239 
5240  ir_graph *const irg = get_irn_irg(block);
5241  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SubSP, mode_T, 5, in);
5242 
5243  /* flags */
5244  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5245  irn_flags |= arch_irn_flag_modify_flags;
5246 
5247  /* init node attributes */
5248  int const n_res = 3;
5249  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5250  (void)attr; /* avoid potential warning */
5251  x86_insn_size_t size = X86_SIZE_32;
5252  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5253  set_ia32_am_support(res, ia32_am_binary);
5254  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5255  out_infos[0].req = &ia32_requirements_gp_esp_I;
5256  out_infos[1].req = &ia32_class_reg_req_gp;
5257  out_infos[2].req = &arch_memory_requirement;
5258 
5259  verify_new_node(res);
5260  return optimize_node(res);
5261 }
5262 
5263 ir_node *new_bd_ia32_Subs(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, x86_insn_size_t size)
5264 {
5265  static arch_register_req_t const *in_reqs[] = {
5266  &ia32_class_reg_req_gp,
5267  &ia32_class_reg_req_gp,
5268  &arch_memory_requirement,
5269  &ia32_class_reg_req_xmm,
5270  &ia32_class_reg_req_xmm,
5271  };
5272 
5273  /* construct in array */
5274  ir_node *const in[] = {
5275  base,
5276  index,
5277  mem,
5278  minuend,
5279  subtrahend,
5280  };
5281 
5282  ir_graph *const irg = get_irn_irg(block);
5283  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Subs, ia32_mode_float64, 5, in);
5284 
5285  /* flags */
5286  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5287  irn_flags |= arch_irn_flag_rematerializable;
5288 
5289  /* init node attributes */
5290  int const n_res = 3;
5291  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5292  (void)attr; /* avoid potential warning */
5293  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5294  set_ia32_am_support(res, ia32_am_binary);
5295  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5296  out_infos[0].req = &ia32_requirements_xmm_in_r3;
5297  out_infos[1].req = &ia32_class_reg_req_flags;
5298  out_infos[2].req = &arch_memory_requirement;
5299 
5300  verify_new_node(res);
5301  return optimize_node(res);
5302 }
5303 
5304 ir_node *new_bd_ia32_SwitchJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, int n_res, const ir_switch_table *switch_table, const ir_entity *table_entity)
5305 {
5306  static arch_register_req_t const *in_reqs[] = {
5307  &ia32_class_reg_req_gp,
5308  &ia32_class_reg_req_gp,
5309  };
5310 
5311  /* construct in array */
5312  ir_node *const in[] = {
5313  base,
5314  index,
5315  };
5316 
5317  ir_graph *const irg = get_irn_irg(block);
5318  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_SwitchJmp, mode_T, 2, in);
5319 
5320  /* flags */
5321  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5322 
5323  /* init node attributes */
5324  ia32_switch_attr_t *const attr = (ia32_switch_attr_t*)get_irn_generic_attr(res);
5325  (void)attr; /* avoid potential warning */
5326  x86_insn_size_t const size = X86_SIZE_32;
5327  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5328  init_ia32_switch_attributes(res, switch_table, table_entity);
5329 
5330  verify_new_node(res);
5331  return optimize_node(res);
5332 }
5333 
5334 ir_node *new_bd_ia32_Test(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted)
5335 {
5336  static arch_register_req_t const *in_reqs[] = {
5337  &ia32_class_reg_req_gp,
5338  &ia32_class_reg_req_gp,
5339  &arch_memory_requirement,
5340  &ia32_class_reg_req_gp,
5341  &ia32_class_reg_req_gp,
5342  };
5343 
5344  /* construct in array */
5345  ir_node *const in[] = {
5346  base,
5347  index,
5348  mem,
5349  left,
5350  right,
5351  };
5352 
5353  ir_graph *const irg = get_irn_irg(block);
5354  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Test, ia32_mode_flags, 5, in);
5355 
5356  /* flags */
5357  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5358  irn_flags |= arch_irn_flag_modify_flags;
5359  irn_flags |= arch_irn_flag_rematerializable;
5360 
5361  /* init node attributes */
5362  int const n_res = 3;
5363  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5364  (void)attr; /* avoid potential warning */
5365  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5366  set_ia32_am_support(res, ia32_am_binary);
5367  attr->ins_permuted = ins_permuted;
5368  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5369  out_infos[0].req = &ia32_class_reg_req_flags;
5370  out_infos[1].req = &arch_no_requirement;
5371  out_infos[2].req = &arch_memory_requirement;
5372 
5373  verify_new_node(res);
5374  return optimize_node(res);
5375 }
5376 
5377 ir_node *new_bd_ia32_Test_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size, bool ins_permuted)
5378 {
5379  static arch_register_req_t const *in_reqs[] = {
5380  &ia32_class_reg_req_gp,
5381  &ia32_class_reg_req_gp,
5382  &arch_memory_requirement,
5383  &ia32_requirements_gp_eax_ebx_ecx_edx,
5384  &ia32_requirements_gp_eax_ebx_ecx_edx,
5385  };
5386 
5387  /* construct in array */
5388  ir_node *const in[] = {
5389  base,
5390  index,
5391  mem,
5392  left,
5393  right,
5394  };
5395 
5396  ir_graph *const irg = get_irn_irg(block);
5397  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Test, ia32_mode_flags, 5, in);
5398 
5399  /* flags */
5400  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5401  irn_flags |= arch_irn_flag_modify_flags;
5402  irn_flags |= arch_irn_flag_rematerializable;
5403 
5404  /* init node attributes */
5405  int const n_res = 3;
5406  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5407  (void)attr; /* avoid potential warning */
5408  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5409  set_ia32_am_support(res, ia32_am_binary);
5410  attr->ins_permuted = ins_permuted;
5411  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5412  out_infos[0].req = &ia32_class_reg_req_flags;
5413  out_infos[1].req = &arch_no_requirement;
5414  out_infos[2].req = &arch_memory_requirement;
5415 
5416  verify_new_node(res);
5417  return optimize_node(res);
5418 }
5419 
5420 ir_node *new_bd_ia32_UD2(dbg_info *dbgi, ir_node *block, ir_node *mem)
5421 {
5422  static arch_register_req_t const *in_reqs[] = {
5423  &arch_memory_requirement,
5424  };
5425 
5426  /* construct in array */
5427  ir_node *const in[] = {
5428  mem,
5429  };
5430 
5431  ir_graph *const irg = get_irn_irg(block);
5432  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_UD2, mode_M, 1, in);
5433 
5434  /* flags */
5435  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5436 
5437  /* init node attributes */
5438  int const n_res = 1;
5439  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5440  (void)attr; /* avoid potential warning */
5441  x86_insn_size_t const size = X86_SIZE_32;
5442  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5443  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5444  out_infos[0].req = &arch_memory_requirement;
5445 
5446  verify_new_node(res);
5447  return optimize_node(res);
5448 }
5449 
5450 ir_node *new_bd_ia32_Ucomis(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted)
5451 {
5452  static arch_register_req_t const *in_reqs[] = {
5453  &ia32_class_reg_req_gp,
5454  &ia32_class_reg_req_gp,
5455  &arch_memory_requirement,
5456  &ia32_class_reg_req_xmm,
5457  &ia32_class_reg_req_xmm,
5458  };
5459 
5460  /* construct in array */
5461  ir_node *const in[] = {
5462  base,
5463  index,
5464  mem,
5465  left,
5466  right,
5467  };
5468 
5469  ir_graph *const irg = get_irn_irg(block);
5470  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Ucomis, ia32_mode_flags, 5, in);
5471 
5472  /* flags */
5473  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5474  irn_flags |= arch_irn_flag_modify_flags;
5475  irn_flags |= arch_irn_flag_rematerializable;
5476 
5477  /* init node attributes */
5478  int const n_res = 1;
5479  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5480  (void)attr; /* avoid potential warning */
5481  x86_insn_size_t const size = X86_SIZE_32;
5482  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5483  set_ia32_am_support(res, ia32_am_binary);
5484  attr->ins_permuted = ins_permuted;
5485  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5486  out_infos[0].req = &ia32_single_reg_req_flags_eflags;
5487 
5488  verify_new_node(res);
5489  return optimize_node(res);
5490 }
5491 
5492 ir_node *new_bd_ia32_Xor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
5493 {
5494  static arch_register_req_t const *in_reqs[] = {
5495  &ia32_class_reg_req_gp,
5496  &ia32_class_reg_req_gp,
5497  &arch_memory_requirement,
5498  &ia32_class_reg_req_gp,
5499  &ia32_class_reg_req_gp,
5500  };
5501 
5502  /* construct in array */
5503  ir_node *const in[] = {
5504  base,
5505  index,
5506  mem,
5507  left,
5508  right,
5509  };
5510 
5511  ir_graph *const irg = get_irn_irg(block);
5512  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Xor, ia32_mode_gp, 5, in);
5513 
5514  /* flags */
5515  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5516  irn_flags |= arch_irn_flag_modify_flags;
5517  irn_flags |= arch_irn_flag_rematerializable;
5518 
5519  /* init node attributes */
5520  int const n_res = 3;
5521  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5522  (void)attr; /* avoid potential warning */
5523  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5524  set_ia32_am_support(res, ia32_am_binary);
5525  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5526  out_infos[0].req = &ia32_requirements_gp_in_r3_in_r4;
5527  out_infos[1].req = &ia32_class_reg_req_flags;
5528  out_infos[2].req = &arch_memory_requirement;
5529 
5530  verify_new_node(res);
5531  return optimize_node(res);
5532 }
5533 
5534 ir_node *new_bd_ia32_Xor_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
5535 {
5536  static arch_register_req_t const *in_reqs[] = {
5537  &ia32_class_reg_req_gp,
5538  &ia32_class_reg_req_gp,
5539  &arch_memory_requirement,
5540  &ia32_requirements_gp_eax_ebx_ecx_edx,
5541  &ia32_requirements_gp_eax_ebx_ecx_edx,
5542  };
5543 
5544  /* construct in array */
5545  ir_node *const in[] = {
5546  base,
5547  index,
5548  mem,
5549  left,
5550  right,
5551  };
5552 
5553  ir_graph *const irg = get_irn_irg(block);
5554  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Xor, ia32_mode_gp, 5, in);
5555 
5556  /* flags */
5557  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5558  irn_flags |= arch_irn_flag_modify_flags;
5559  irn_flags |= arch_irn_flag_rematerializable;
5560 
5561  /* init node attributes */
5562  int const n_res = 3;
5563  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5564  (void)attr; /* avoid potential warning */
5565  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5566  set_ia32_am_support(res, ia32_am_binary);
5567  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5568  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r3_in_r4;
5569  out_infos[1].req = &ia32_class_reg_req_flags;
5570  out_infos[2].req = &arch_memory_requirement;
5571 
5572  verify_new_node(res);
5573  return optimize_node(res);
5574 }
5575 
5576 ir_node *new_bd_ia32_Xor0(dbg_info *dbgi, ir_node *block, x86_insn_size_t size)
5577 {
5578  arch_register_req_t const **const in_reqs = NULL;
5579 
5580 
5581  ir_graph *const irg = get_irn_irg(block);
5582  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Xor0, ia32_mode_gp, 0, NULL);
5583 
5584  /* flags */
5585  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5586  irn_flags |= arch_irn_flag_modify_flags;
5587  irn_flags |= arch_irn_flag_rematerializable;
5588 
5589  /* init node attributes */
5590  int const n_res = 2;
5591  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5592  (void)attr; /* avoid potential warning */
5593  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5594  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5595  out_infos[0].req = &ia32_class_reg_req_gp;
5596  out_infos[1].req = &ia32_class_reg_req_flags;
5597 
5598  verify_new_node(res);
5599  return optimize_node(res);
5600 }
5601 
5602 ir_node *new_bd_ia32_XorHighLow(dbg_info *dbgi, ir_node *block, ir_node *value)
5603 {
5604  static arch_register_req_t const *in_reqs[] = {
5605  &ia32_requirements_gp_eax_ebx_ecx_edx,
5606  };
5607 
5608  /* construct in array */
5609  ir_node *const in[] = {
5610  value,
5611  };
5612 
5613  ir_graph *const irg = get_irn_irg(block);
5614  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_XorHighLow, mode_T, 1, in);
5615 
5616  /* flags */
5617  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5618  irn_flags |= arch_irn_flag_modify_flags;
5619  irn_flags |= arch_irn_flag_rematerializable;
5620 
5621  /* init node attributes */
5622  int const n_res = 2;
5623  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5624  (void)attr; /* avoid potential warning */
5625  x86_insn_size_t const size = X86_SIZE_8;
5626  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5627  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5628  out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx_in_r0;
5629  out_infos[1].req = &ia32_class_reg_req_flags;
5630 
5631  verify_new_node(res);
5632  return optimize_node(res);
5633 }
5634 
5635 ir_node *new_bd_ia32_XorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5636 {
5637  static arch_register_req_t const *in_reqs[] = {
5638  &ia32_class_reg_req_gp,
5639  &ia32_class_reg_req_gp,
5640  &arch_memory_requirement,
5641  &ia32_class_reg_req_gp,
5642  };
5643 
5644  /* construct in array */
5645  ir_node *const in[] = {
5646  base,
5647  index,
5648  mem,
5649  val,
5650  };
5651 
5652  ir_graph *const irg = get_irn_irg(block);
5653  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_XorMem, mode_T, 4, in);
5654 
5655  /* flags */
5656  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5657  irn_flags |= arch_irn_flag_modify_flags;
5658  irn_flags |= arch_irn_flag_rematerializable;
5659 
5660  /* init node attributes */
5661  int const n_res = 3;
5662  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5663  (void)attr; /* avoid potential warning */
5664  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5665  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5666  out_infos[0].req = &arch_no_requirement;
5667  out_infos[1].req = &ia32_class_reg_req_flags;
5668  out_infos[2].req = &arch_memory_requirement;
5669 
5670  verify_new_node(res);
5671  return optimize_node(res);
5672 }
5673 
5674 ir_node *new_bd_ia32_XorMem_8bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
5675 {
5676  static arch_register_req_t const *in_reqs[] = {
5677  &ia32_class_reg_req_gp,
5678  &ia32_class_reg_req_gp,
5679  &arch_memory_requirement,
5680  &ia32_requirements_gp_eax_ebx_ecx_edx,
5681  };
5682 
5683  /* construct in array */
5684  ir_node *const in[] = {
5685  base,
5686  index,
5687  mem,
5688  val,
5689  };
5690 
5691  ir_graph *const irg = get_irn_irg(block);
5692  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_XorMem, mode_T, 4, in);
5693 
5694  /* flags */
5695  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5696  irn_flags |= arch_irn_flag_modify_flags;
5697  irn_flags |= arch_irn_flag_rematerializable;
5698 
5699  /* init node attributes */
5700  int const n_res = 3;
5701  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5702  (void)attr; /* avoid potential warning */
5703  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5704  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5705  out_infos[0].req = &arch_no_requirement;
5706  out_infos[1].req = &ia32_class_reg_req_flags;
5707  out_infos[2].req = &arch_memory_requirement;
5708 
5709  verify_new_node(res);
5710  return optimize_node(res);
5711 }
5712 
5713 ir_node *new_bd_ia32_Xorp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, x86_insn_size_t size)
5714 {
5715  static arch_register_req_t const *in_reqs[] = {
5716  &ia32_class_reg_req_gp,
5717  &ia32_class_reg_req_gp,
5718  &arch_memory_requirement,
5719  &ia32_class_reg_req_xmm,
5720  &ia32_class_reg_req_xmm,
5721  };
5722 
5723  /* construct in array */
5724  ir_node *const in[] = {
5725  base,
5726  index,
5727  mem,
5728  left,
5729  right,
5730  };
5731 
5732  ir_graph *const irg = get_irn_irg(block);
5733  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_Xorp, ia32_mode_float64, 5, in);
5734 
5735  /* flags */
5736  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5737  irn_flags |= arch_irn_flag_rematerializable;
5738 
5739  /* init node attributes */
5740  int const n_res = 3;
5741  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5742  (void)attr; /* avoid potential warning */
5743  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5744  set_ia32_am_support(res, ia32_am_binary);
5745  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5746  out_infos[0].req = &ia32_requirements_xmm_in_r3_in_r4;
5747  out_infos[1].req = &ia32_class_reg_req_flags;
5748  out_infos[2].req = &arch_memory_requirement;
5749 
5750  verify_new_node(res);
5751  return optimize_node(res);
5752 }
5753 
5754 ir_node *new_bd_ia32_emms(dbg_info *dbgi, ir_node *block)
5755 {
5756  arch_register_req_t const **const in_reqs = NULL;
5757 
5758 
5759  ir_graph *const irg = get_irn_irg(block);
5760  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_emms, mode_ANY, 0, NULL);
5761 
5762  /* flags */
5763  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5764 
5765  /* init node attributes */
5766  int const n_res = 1;
5767  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5768  (void)attr; /* avoid potential warning */
5769  x86_insn_size_t const size = X86_SIZE_32; ia32_request_x87_sim(irg);
5770  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5771  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5772  out_infos[0].req = &arch_no_requirement;
5773 
5774  verify_new_node(res);
5775  return optimize_node(res);
5776 }
5777 
5778 ir_node *new_bd_ia32_fabs(dbg_info *dbgi, ir_node *block, ir_node *value)
5779 {
5780  static arch_register_req_t const *in_reqs[] = {
5781  &ia32_class_reg_req_fp,
5782  };
5783 
5784  /* construct in array */
5785  ir_node *const in[] = {
5786  value,
5787  };
5788 
5789  ir_graph *const irg = get_irn_irg(block);
5790  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fabs, x86_mode_E, 1, in);
5791 
5792  /* flags */
5793  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5794  irn_flags |= arch_irn_flag_rematerializable;
5795 
5796  /* init node attributes */
5797  int const n_res = 1;
5798  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5799  (void)attr; /* avoid potential warning */
5800  x86_insn_size_t const size = X86_SIZE_80;
5801  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5802  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5803  out_infos[0].req = &ia32_class_reg_req_fp;
5804 
5805  verify_new_node(res);
5806  return optimize_node(res);
5807 }
5808 
5809 ir_node *new_bd_ia32_fadd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size)
5810 {
5811  static arch_register_req_t const *in_reqs[] = {
5812  &ia32_class_reg_req_gp,
5813  &ia32_class_reg_req_gp,
5814  &arch_memory_requirement,
5815  &ia32_class_reg_req_fp,
5816  &ia32_class_reg_req_fp,
5817  &ia32_single_reg_req_fp_cw_fpcw,
5818  };
5819 
5820  /* construct in array */
5821  ir_node *const in[] = {
5822  base,
5823  index,
5824  mem,
5825  left,
5826  right,
5827  fpcw,
5828  };
5829 
5830  ir_graph *const irg = get_irn_irg(block);
5831  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fadd, x86_mode_E, 6, in);
5832 
5833  /* flags */
5834  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5835 
5836  /* init node attributes */
5837  int const n_res = 3;
5838  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
5839  (void)attr; /* avoid potential warning */
5840  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5841  init_ia32_x87_attributes(res);
5842  set_ia32_am_support(res, ia32_am_binary);
5843  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5844  out_infos[0].req = &ia32_class_reg_req_fp;
5845  out_infos[1].req = &arch_no_requirement;
5846  out_infos[2].req = &arch_memory_requirement;
5847 
5848  verify_new_node(res);
5849  return optimize_node(res);
5850 }
5851 
5852 ir_node *new_bd_ia32_fchs(dbg_info *dbgi, ir_node *block, ir_node *value)
5853 {
5854  static arch_register_req_t const *in_reqs[] = {
5855  &ia32_class_reg_req_fp,
5856  };
5857 
5858  /* construct in array */
5859  ir_node *const in[] = {
5860  value,
5861  };
5862 
5863  ir_graph *const irg = get_irn_irg(block);
5864  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fchs, x86_mode_E, 1, in);
5865 
5866  /* flags */
5867  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5868  irn_flags |= arch_irn_flag_rematerializable;
5869 
5870  /* init node attributes */
5871  int const n_res = 1;
5872  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5873  (void)attr; /* avoid potential warning */
5874  x86_insn_size_t const size = X86_SIZE_80;
5875  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5876  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5877  out_infos[0].req = &ia32_class_reg_req_fp;
5878 
5879  verify_new_node(res);
5880  return optimize_node(res);
5881 }
5882 
5883 ir_node *new_bd_ia32_fdiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size)
5884 {
5885  static arch_register_req_t const *in_reqs[] = {
5886  &ia32_class_reg_req_gp,
5887  &ia32_class_reg_req_gp,
5888  &arch_memory_requirement,
5889  &ia32_class_reg_req_fp,
5890  &ia32_class_reg_req_fp,
5891  &ia32_single_reg_req_fp_cw_fpcw,
5892  };
5893 
5894  /* construct in array */
5895  ir_node *const in[] = {
5896  base,
5897  index,
5898  mem,
5899  left,
5900  right,
5901  fpcw,
5902  };
5903 
5904  ir_graph *const irg = get_irn_irg(block);
5905  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fdiv, mode_T, 6, in);
5906 
5907  /* flags */
5908  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5909 
5910  /* init node attributes */
5911  int const n_res = 3;
5912  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
5913  (void)attr; /* avoid potential warning */
5914  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5915  init_ia32_x87_attributes(res);
5916  set_ia32_am_support(res, ia32_am_binary);
5917  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5918  out_infos[0].req = &ia32_class_reg_req_fp;
5919  out_infos[1].req = &arch_no_requirement;
5920  out_infos[2].req = &arch_memory_requirement;
5921 
5922  verify_new_node(res);
5923  return optimize_node(res);
5924 }
5925 
5926 ir_node *new_bd_ia32_fdup(dbg_info *dbgi, ir_node *block, ir_node *val, const arch_register_t *reg)
5927 {
5928  static arch_register_req_t const *in_reqs[] = {
5929  &ia32_class_reg_req_fp,
5930  };
5931 
5932  /* construct in array */
5933  ir_node *const in[] = {
5934  val,
5935  };
5936 
5937  ir_graph *const irg = get_irn_irg(block);
5938  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fdup, x86_mode_E, 1, in);
5939 
5940  /* flags */
5941  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5942 
5943  /* init node attributes */
5944  int const n_res = 1;
5945  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
5946  (void)attr; /* avoid potential warning */
5947  x86_insn_size_t const size = X86_SIZE_80;
5948  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5949  init_ia32_x87_attributes(res);
5950  attr->x87.reg = reg;
5951  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5952  out_infos[0].req = &ia32_class_reg_req_fp;
5953 
5954  verify_new_node(res);
5955  return optimize_node(res);
5956 }
5957 
5958 ir_node *new_bd_ia32_femms(dbg_info *dbgi, ir_node *block)
5959 {
5960  arch_register_req_t const **const in_reqs = NULL;
5961 
5962 
5963  ir_graph *const irg = get_irn_irg(block);
5964  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_femms, mode_ANY, 0, NULL);
5965 
5966  /* flags */
5967  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5968 
5969  /* init node attributes */
5970  int const n_res = 1;
5971  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
5972  (void)attr; /* avoid potential warning */
5973  x86_insn_size_t const size = X86_SIZE_32; ia32_request_x87_sim(irg);
5974  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5975  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
5976  out_infos[0].req = &arch_no_requirement;
5977 
5978  verify_new_node(res);
5979  return optimize_node(res);
5980 }
5981 
5982 ir_node *new_bd_ia32_ffreep(dbg_info *dbgi, ir_node *block, const arch_register_t *reg)
5983 {
5984  arch_register_req_t const **const in_reqs = NULL;
5985 
5986 
5987  ir_graph *const irg = get_irn_irg(block);
5988  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_ffreep, mode_ANY, 0, NULL);
5989 
5990  /* flags */
5991  arch_irn_flags_t irn_flags = arch_irn_flags_none;
5992 
5993  /* init node attributes */
5994  int const n_res = 1;
5995  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
5996  (void)attr; /* avoid potential warning */
5997  x86_insn_size_t const size = X86_SIZE_80;
5998  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
5999  init_ia32_x87_attributes(res);
6000  attr->x87.reg = reg;
6001  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6002  out_infos[0].req = &arch_no_requirement;
6003 
6004  verify_new_node(res);
6005  return optimize_node(res);
6006 }
6007 
6008 ir_node *new_bd_ia32_fild(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
6009 {
6010  static arch_register_req_t const *in_reqs[] = {
6011  &ia32_class_reg_req_gp,
6012  &ia32_class_reg_req_gp,
6013  &arch_memory_requirement,
6014  };
6015 
6016  /* construct in array */
6017  ir_node *const in[] = {
6018  base,
6019  index,
6020  mem,
6021  };
6022 
6023  ir_graph *const irg = get_irn_irg(block);
6024  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fild, mode_T, 3, in);
6025 
6026  /* flags */
6027  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6028 
6029  /* init node attributes */
6030  int const n_res = 3;
6031  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6032  (void)attr; /* avoid potential warning */
6033  ia32_request_x87_sim(irg);
6034  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6035  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6036  out_infos[0].req = &ia32_class_reg_req_fp;
6037  out_infos[1].req = &arch_no_requirement;
6038  out_infos[2].req = &arch_memory_requirement;
6039 
6040  verify_new_node(res);
6041  return optimize_node(res);
6042 }
6043 
6044 ir_node *new_bd_ia32_fist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw, x86_insn_size_t size)
6045 {
6046  static arch_register_req_t const *in_reqs[] = {
6047  &ia32_class_reg_req_gp,
6048  &ia32_class_reg_req_gp,
6049  &arch_memory_requirement,
6050  &ia32_class_reg_req_fp,
6051  &ia32_single_reg_req_fp_cw_fpcw,
6052  };
6053 
6054  /* construct in array */
6055  ir_node *const in[] = {
6056  base,
6057  index,
6058  mem,
6059  val,
6060  fpcw,
6061  };
6062 
6063  ir_graph *const irg = get_irn_irg(block);
6064  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fist, mode_T, 5, in);
6065 
6066  /* flags */
6067  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6068 
6069  /* init node attributes */
6070  int const n_res = 3;
6071  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6072  (void)attr; /* avoid potential warning */
6073  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6074  init_ia32_x87_attributes(res);
6075  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6076  out_infos[0].req = &arch_memory_requirement;
6077  out_infos[1].req = &arch_exec_requirement;
6078  out_infos[2].req = &arch_exec_requirement;
6079 
6080  verify_new_node(res);
6081  return optimize_node(res);
6082 }
6083 
6084 ir_node *new_bd_ia32_fistp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw, x86_insn_size_t size)
6085 {
6086  static arch_register_req_t const *in_reqs[] = {
6087  &ia32_class_reg_req_gp,
6088  &ia32_class_reg_req_gp,
6089  &arch_memory_requirement,
6090  &ia32_requirements_fp_fp_K,
6091  &ia32_single_reg_req_fp_cw_fpcw,
6092  };
6093 
6094  /* construct in array */
6095  ir_node *const in[] = {
6096  base,
6097  index,
6098  mem,
6099  val,
6100  fpcw,
6101  };
6102 
6103  ir_graph *const irg = get_irn_irg(block);
6104  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fistp, mode_T, 5, in);
6105 
6106  /* flags */
6107  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6108 
6109  /* init node attributes */
6110  int const n_res = 3;
6111  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6112  (void)attr; /* avoid potential warning */
6113  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6114  init_ia32_x87_attributes(res);
6115  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6116  out_infos[0].req = &arch_memory_requirement;
6117  out_infos[1].req = &arch_exec_requirement;
6118  out_infos[2].req = &arch_exec_requirement;
6119 
6120  verify_new_node(res);
6121  return optimize_node(res);
6122 }
6123 
6124 ir_node *new_bd_ia32_fisttp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
6125 {
6126  static arch_register_req_t const *in_reqs[] = {
6127  &ia32_class_reg_req_gp,
6128  &ia32_class_reg_req_gp,
6129  &arch_memory_requirement,
6130  &ia32_requirements_fp_fp_K,
6131  };
6132 
6133  /* construct in array */
6134  ir_node *const in[] = {
6135  base,
6136  index,
6137  mem,
6138  val,
6139  };
6140 
6141  ir_graph *const irg = get_irn_irg(block);
6142  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fisttp, mode_T, 4, in);
6143 
6144  /* flags */
6145  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6146 
6147  /* init node attributes */
6148  int const n_res = 3;
6149  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6150  (void)attr; /* avoid potential warning */
6151  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6152  init_ia32_x87_attributes(res);
6153  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6154  out_infos[0].req = &arch_memory_requirement;
6155  out_infos[1].req = &arch_exec_requirement;
6156  out_infos[2].req = &arch_exec_requirement;
6157 
6158  verify_new_node(res);
6159  return optimize_node(res);
6160 }
6161 
6162 ir_node *new_bd_ia32_fld(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
6163 {
6164  static arch_register_req_t const *in_reqs[] = {
6165  &ia32_class_reg_req_gp,
6166  &ia32_class_reg_req_gp,
6167  &arch_memory_requirement,
6168  };
6169 
6170  /* construct in array */
6171  ir_node *const in[] = {
6172  base,
6173  index,
6174  mem,
6175  };
6176 
6177  ir_graph *const irg = get_irn_irg(block);
6178  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fld, mode_T, 3, in);
6179 
6180  /* flags */
6181  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6182  irn_flags |= arch_irn_flag_rematerializable;
6183 
6184  /* init node attributes */
6185  int const n_res = 5;
6186  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6187  (void)attr; /* avoid potential warning */
6188  ia32_request_x87_sim(irg);
6189  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6190  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6191  out_infos[0].req = &ia32_class_reg_req_fp;
6192  out_infos[1].req = &arch_no_requirement;
6193  out_infos[2].req = &arch_memory_requirement;
6194  out_infos[3].req = &arch_exec_requirement;
6195  out_infos[4].req = &arch_exec_requirement;
6196 
6197  verify_new_node(res);
6198  return optimize_node(res);
6199 }
6200 
6201 ir_node *new_bd_ia32_fld1(dbg_info *dbgi, ir_node *block)
6202 {
6203  arch_register_req_t const **const in_reqs = NULL;
6204 
6205 
6206  ir_graph *const irg = get_irn_irg(block);
6207  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fld1, x86_mode_E, 0, NULL);
6208 
6209  /* flags */
6210  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6211  irn_flags |= arch_irn_flag_rematerializable;
6212 
6213  /* init node attributes */
6214  int const n_res = 1;
6215  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6216  (void)attr; /* avoid potential warning */
6217  x86_insn_size_t const size = X86_SIZE_80;
6218  ia32_request_x87_sim(irg);
6219  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6220  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6221  out_infos[0].req = &ia32_class_reg_req_fp;
6222 
6223  verify_new_node(res);
6224  return optimize_node(res);
6225 }
6226 
6227 ir_node *new_bd_ia32_fldl2e(dbg_info *dbgi, ir_node *block)
6228 {
6229  arch_register_req_t const **const in_reqs = NULL;
6230 
6231 
6232  ir_graph *const irg = get_irn_irg(block);
6233  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldl2e, x86_mode_E, 0, NULL);
6234 
6235  /* flags */
6236  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6237  irn_flags |= arch_irn_flag_rematerializable;
6238 
6239  /* init node attributes */
6240  int const n_res = 1;
6241  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6242  (void)attr; /* avoid potential warning */
6243  x86_insn_size_t const size = X86_SIZE_80;
6244  ia32_request_x87_sim(irg);
6245  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6246  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6247  out_infos[0].req = &ia32_class_reg_req_fp;
6248 
6249  verify_new_node(res);
6250  return optimize_node(res);
6251 }
6252 
6253 ir_node *new_bd_ia32_fldl2t(dbg_info *dbgi, ir_node *block)
6254 {
6255  arch_register_req_t const **const in_reqs = NULL;
6256 
6257 
6258  ir_graph *const irg = get_irn_irg(block);
6259  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldl2t, x86_mode_E, 0, NULL);
6260 
6261  /* flags */
6262  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6263  irn_flags |= arch_irn_flag_rematerializable;
6264 
6265  /* init node attributes */
6266  int const n_res = 1;
6267  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6268  (void)attr; /* avoid potential warning */
6269  x86_insn_size_t const size = X86_SIZE_80;
6270  ia32_request_x87_sim(irg);
6271  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6272  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6273  out_infos[0].req = &ia32_class_reg_req_fp;
6274 
6275  verify_new_node(res);
6276  return optimize_node(res);
6277 }
6278 
6279 ir_node *new_bd_ia32_fldlg2(dbg_info *dbgi, ir_node *block)
6280 {
6281  arch_register_req_t const **const in_reqs = NULL;
6282 
6283 
6284  ir_graph *const irg = get_irn_irg(block);
6285  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldlg2, x86_mode_E, 0, NULL);
6286 
6287  /* flags */
6288  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6289  irn_flags |= arch_irn_flag_rematerializable;
6290 
6291  /* init node attributes */
6292  int const n_res = 1;
6293  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6294  (void)attr; /* avoid potential warning */
6295  x86_insn_size_t const size = X86_SIZE_80;
6296  ia32_request_x87_sim(irg);
6297  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6298  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6299  out_infos[0].req = &ia32_class_reg_req_fp;
6300 
6301  verify_new_node(res);
6302  return optimize_node(res);
6303 }
6304 
6305 ir_node *new_bd_ia32_fldln2(dbg_info *dbgi, ir_node *block)
6306 {
6307  arch_register_req_t const **const in_reqs = NULL;
6308 
6309 
6310  ir_graph *const irg = get_irn_irg(block);
6311  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldln2, x86_mode_E, 0, NULL);
6312 
6313  /* flags */
6314  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6315  irn_flags |= arch_irn_flag_rematerializable;
6316 
6317  /* init node attributes */
6318  int const n_res = 1;
6319  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6320  (void)attr; /* avoid potential warning */
6321  x86_insn_size_t const size = X86_SIZE_80;
6322  ia32_request_x87_sim(irg);
6323  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6324  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6325  out_infos[0].req = &ia32_class_reg_req_fp;
6326 
6327  verify_new_node(res);
6328  return optimize_node(res);
6329 }
6330 
6331 ir_node *new_bd_ia32_fldpi(dbg_info *dbgi, ir_node *block)
6332 {
6333  arch_register_req_t const **const in_reqs = NULL;
6334 
6335 
6336  ir_graph *const irg = get_irn_irg(block);
6337  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldpi, x86_mode_E, 0, NULL);
6338 
6339  /* flags */
6340  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6341  irn_flags |= arch_irn_flag_rematerializable;
6342 
6343  /* init node attributes */
6344  int const n_res = 1;
6345  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6346  (void)attr; /* avoid potential warning */
6347  x86_insn_size_t const size = X86_SIZE_80;
6348  ia32_request_x87_sim(irg);
6349  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6350  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6351  out_infos[0].req = &ia32_class_reg_req_fp;
6352 
6353  verify_new_node(res);
6354  return optimize_node(res);
6355 }
6356 
6357 ir_node *new_bd_ia32_fldz(dbg_info *dbgi, ir_node *block)
6358 {
6359  arch_register_req_t const **const in_reqs = NULL;
6360 
6361 
6362  ir_graph *const irg = get_irn_irg(block);
6363  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fldz, x86_mode_E, 0, NULL);
6364 
6365  /* flags */
6366  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6367  irn_flags |= arch_irn_flag_rematerializable;
6368 
6369  /* init node attributes */
6370  int const n_res = 1;
6371  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6372  (void)attr; /* avoid potential warning */
6373  x86_insn_size_t const size = X86_SIZE_80;
6374  ia32_request_x87_sim(irg);
6375  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6376  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6377  out_infos[0].req = &ia32_class_reg_req_fp;
6378 
6379  verify_new_node(res);
6380  return optimize_node(res);
6381 }
6382 
6383 ir_node *new_bd_ia32_fmul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size)
6384 {
6385  static arch_register_req_t const *in_reqs[] = {
6386  &ia32_class_reg_req_gp,
6387  &ia32_class_reg_req_gp,
6388  &arch_memory_requirement,
6389  &ia32_class_reg_req_fp,
6390  &ia32_class_reg_req_fp,
6391  &ia32_single_reg_req_fp_cw_fpcw,
6392  };
6393 
6394  /* construct in array */
6395  ir_node *const in[] = {
6396  base,
6397  index,
6398  mem,
6399  left,
6400  right,
6401  fpcw,
6402  };
6403 
6404  ir_graph *const irg = get_irn_irg(block);
6405  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fmul, x86_mode_E, 6, in);
6406 
6407  /* flags */
6408  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6409 
6410  /* init node attributes */
6411  int const n_res = 3;
6412  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6413  (void)attr; /* avoid potential warning */
6414  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6415  init_ia32_x87_attributes(res);
6416  set_ia32_am_support(res, ia32_am_binary);
6417  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6418  out_infos[0].req = &ia32_class_reg_req_fp;
6419  out_infos[1].req = &arch_no_requirement;
6420  out_infos[2].req = &arch_memory_requirement;
6421 
6422  verify_new_node(res);
6423  return optimize_node(res);
6424 }
6425 
6426 ir_node *new_bd_ia32_fpop(dbg_info *dbgi, ir_node *block, const arch_register_t *reg)
6427 {
6428  arch_register_req_t const **const in_reqs = NULL;
6429 
6430 
6431  ir_graph *const irg = get_irn_irg(block);
6432  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fpop, mode_ANY, 0, NULL);
6433 
6434  /* flags */
6435  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6436 
6437  /* init node attributes */
6438  int const n_res = 1;
6439  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6440  (void)attr; /* avoid potential warning */
6441  x86_insn_size_t const size = X86_SIZE_80;
6442  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6443  init_ia32_x87_attributes(res);
6444  attr->x87.reg = reg;
6445  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6446  out_infos[0].req = &arch_no_requirement;
6447 
6448  verify_new_node(res);
6449  return optimize_node(res);
6450 }
6451 
6452 ir_node *new_bd_ia32_fst(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
6453 {
6454  static arch_register_req_t const *in_reqs[] = {
6455  &ia32_class_reg_req_gp,
6456  &ia32_class_reg_req_gp,
6457  &arch_memory_requirement,
6458  &ia32_class_reg_req_fp,
6459  };
6460 
6461  /* construct in array */
6462  ir_node *const in[] = {
6463  base,
6464  index,
6465  mem,
6466  val,
6467  };
6468 
6469  ir_graph *const irg = get_irn_irg(block);
6470  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fst, mode_T, 4, in);
6471 
6472  /* flags */
6473  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6474  irn_flags |= arch_irn_flag_rematerializable;
6475 
6476  /* init node attributes */
6477  int const n_res = 3;
6478  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6479  (void)attr; /* avoid potential warning */
6480  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6481  init_ia32_x87_attributes(res);
6482  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6483  out_infos[0].req = &arch_memory_requirement;
6484  out_infos[1].req = &arch_exec_requirement;
6485  out_infos[2].req = &arch_exec_requirement;
6486 
6487  verify_new_node(res);
6488  return optimize_node(res);
6489 }
6490 
6491 ir_node *new_bd_ia32_fstp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
6492 {
6493  static arch_register_req_t const *in_reqs[] = {
6494  &ia32_class_reg_req_gp,
6495  &ia32_class_reg_req_gp,
6496  &arch_memory_requirement,
6497  &ia32_requirements_fp_fp_K,
6498  };
6499 
6500  /* construct in array */
6501  ir_node *const in[] = {
6502  base,
6503  index,
6504  mem,
6505  val,
6506  };
6507 
6508  ir_graph *const irg = get_irn_irg(block);
6509  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fstp, mode_T, 4, in);
6510 
6511  /* flags */
6512  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6513  irn_flags |= arch_irn_flag_rematerializable;
6514 
6515  /* init node attributes */
6516  int const n_res = 3;
6517  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6518  (void)attr; /* avoid potential warning */
6519  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6520  init_ia32_x87_attributes(res);
6521  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6522  out_infos[0].req = &arch_memory_requirement;
6523  out_infos[1].req = &arch_exec_requirement;
6524  out_infos[2].req = &arch_exec_requirement;
6525 
6526  verify_new_node(res);
6527  return optimize_node(res);
6528 }
6529 
6530 ir_node *new_bd_ia32_fsub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw, x86_insn_size_t size)
6531 {
6532  static arch_register_req_t const *in_reqs[] = {
6533  &ia32_class_reg_req_gp,
6534  &ia32_class_reg_req_gp,
6535  &arch_memory_requirement,
6536  &ia32_class_reg_req_fp,
6537  &ia32_class_reg_req_fp,
6538  &ia32_single_reg_req_fp_cw_fpcw,
6539  };
6540 
6541  /* construct in array */
6542  ir_node *const in[] = {
6543  base,
6544  index,
6545  mem,
6546  left,
6547  right,
6548  fpcw,
6549  };
6550 
6551  ir_graph *const irg = get_irn_irg(block);
6552  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fsub, x86_mode_E, 6, in);
6553 
6554  /* flags */
6555  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6556 
6557  /* init node attributes */
6558  int const n_res = 3;
6559  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6560  (void)attr; /* avoid potential warning */
6561  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6562  init_ia32_x87_attributes(res);
6563  set_ia32_am_support(res, ia32_am_binary);
6564  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6565  out_infos[0].req = &ia32_class_reg_req_fp;
6566  out_infos[1].req = &arch_no_requirement;
6567  out_infos[2].req = &arch_memory_requirement;
6568 
6569  verify_new_node(res);
6570  return optimize_node(res);
6571 }
6572 
6573 ir_node *new_bd_ia32_fxch(dbg_info *dbgi, ir_node *block, const arch_register_t *reg)
6574 {
6575  arch_register_req_t const **const in_reqs = NULL;
6576 
6577 
6578  ir_graph *const irg = get_irn_irg(block);
6579  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_fxch, mode_ANY, 0, NULL);
6580 
6581  /* flags */
6582  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6583 
6584  /* init node attributes */
6585  int const n_res = 1;
6586  ia32_x87_attr_t *const attr = (ia32_x87_attr_t*)get_irn_generic_attr(res);
6587  (void)attr; /* avoid potential warning */
6588  x86_insn_size_t const size = X86_SIZE_80;
6589  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6590  init_ia32_x87_attributes(res);
6591  attr->x87.reg = reg;
6592  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6593  out_infos[0].req = &arch_no_requirement;
6594 
6595  verify_new_node(res);
6596  return optimize_node(res);
6597 }
6598 
6599 ir_node *new_bd_ia32_l_Adc(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *eflags, ir_mode *mode)
6600 {
6601 
6602  /* construct in array */
6603  ir_node *const in[] = {
6604  left,
6605  right,
6606  eflags,
6607  };
6608 
6609  ir_graph *const irg = get_irn_irg(block);
6610  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Adc, mode, 3, in);
6611 
6612  /* flags */
6613  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6614 
6615  /* init node attributes */
6616  int const n_res = 0;
6617  (void)irn_flags, (void)n_res;
6618 
6619  verify_new_node(res);
6620  return optimize_node(res);
6621 }
6622 
6623 ir_node *new_bd_ia32_l_Add(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right)
6624 {
6625 
6626  /* construct in array */
6627  ir_node *const in[] = {
6628  left,
6629  right,
6630  };
6631 
6632  ir_graph *const irg = get_irn_irg(block);
6633  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Add, mode_T, 2, in);
6634 
6635  /* flags */
6636  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6637 
6638  /* init node attributes */
6639  int const n_res = 2;
6640  (void)irn_flags, (void)n_res;
6641 
6642  verify_new_node(res);
6643  return optimize_node(res);
6644 }
6645 
6646 ir_node *new_bd_ia32_l_FloattoLL(dbg_info *dbgi, ir_node *block, ir_node *val)
6647 {
6648 
6649  /* construct in array */
6650  ir_node *const in[] = {
6651  val,
6652  };
6653 
6654  ir_graph *const irg = get_irn_irg(block);
6655  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_FloattoLL, mode_T, 1, in);
6656 
6657  /* flags */
6658  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6659 
6660  /* init node attributes */
6661  int const n_res = 2;
6662  (void)irn_flags, (void)n_res;
6663 
6664  verify_new_node(res);
6665  return optimize_node(res);
6666 }
6667 
6668 ir_node *new_bd_ia32_l_IMul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right)
6669 {
6670 
6671  /* construct in array */
6672  ir_node *const in[] = {
6673  left,
6674  right,
6675  };
6676 
6677  ir_graph *const irg = get_irn_irg(block);
6678  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_IMul, mode_T, 2, in);
6679 
6680  /* flags */
6681  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6682 
6683  /* init node attributes */
6684  int const n_res = 4;
6685  (void)irn_flags, (void)n_res;
6686 
6687  verify_new_node(res);
6688  return optimize_node(res);
6689 }
6690 
6691 ir_node *new_bd_ia32_l_LLtoFloat(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_mode *mode)
6692 {
6693 
6694  /* construct in array */
6695  ir_node *const in[] = {
6696  val_high,
6697  val_low,
6698  };
6699 
6700  ir_graph *const irg = get_irn_irg(block);
6701  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_LLtoFloat, mode, 2, in);
6702 
6703  /* flags */
6704  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6705 
6706  /* init node attributes */
6707  int const n_res = 0;
6708  (void)irn_flags, (void)n_res;
6709 
6710  verify_new_node(res);
6711  return optimize_node(res);
6712 }
6713 
6714 ir_node *new_bd_ia32_l_Minus64(dbg_info *dbgi, ir_node *block, ir_node *low, ir_node *high)
6715 {
6716 
6717  /* construct in array */
6718  ir_node *const in[] = {
6719  low,
6720  high,
6721  };
6722 
6723  ir_graph *const irg = get_irn_irg(block);
6724  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Minus64, mode_T, 2, in);
6725 
6726  /* flags */
6727  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6728 
6729  /* init node attributes */
6730  int const n_res = 2;
6731  (void)irn_flags, (void)n_res;
6732 
6733  verify_new_node(res);
6734  return optimize_node(res);
6735 }
6736 
6737 ir_node *new_bd_ia32_l_Mul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right)
6738 {
6739 
6740  /* construct in array */
6741  ir_node *const in[] = {
6742  left,
6743  right,
6744  };
6745 
6746  ir_graph *const irg = get_irn_irg(block);
6747  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Mul, mode_T, 2, in);
6748 
6749  /* flags */
6750  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6751 
6752  /* init node attributes */
6753  int const n_res = 4;
6754  (void)irn_flags, (void)n_res;
6755 
6756  verify_new_node(res);
6757  return optimize_node(res);
6758 }
6759 
6760 ir_node *new_bd_ia32_l_Sbb(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, ir_mode *mode)
6761 {
6762 
6763  /* construct in array */
6764  ir_node *const in[] = {
6765  minuend,
6766  subtrahend,
6767  eflags,
6768  };
6769 
6770  ir_graph *const irg = get_irn_irg(block);
6771  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Sbb, mode, 3, in);
6772 
6773  /* flags */
6774  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6775 
6776  /* init node attributes */
6777  int const n_res = 0;
6778  (void)irn_flags, (void)n_res;
6779 
6780  verify_new_node(res);
6781  return optimize_node(res);
6782 }
6783 
6784 ir_node *new_bd_ia32_l_Sub(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend)
6785 {
6786 
6787  /* construct in array */
6788  ir_node *const in[] = {
6789  minuend,
6790  subtrahend,
6791  };
6792 
6793  ir_graph *const irg = get_irn_irg(block);
6794  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_l_Sub, mode_T, 2, in);
6795 
6796  /* flags */
6797  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6798 
6799  /* init node attributes */
6800  int const n_res = 2;
6801  (void)irn_flags, (void)n_res;
6802 
6803  verify_new_node(res);
6804  return optimize_node(res);
6805 }
6806 
6807 ir_node *new_bd_ia32_xAllOnes(dbg_info *dbgi, ir_node *block, x86_insn_size_t size)
6808 {
6809  arch_register_req_t const **const in_reqs = NULL;
6810 
6811 
6812  ir_graph *const irg = get_irn_irg(block);
6813  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xAllOnes, ia32_mode_float64, 0, NULL);
6814 
6815  /* flags */
6816  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6817  irn_flags |= arch_irn_flag_rematerializable;
6818 
6819  /* init node attributes */
6820  int const n_res = 1;
6821  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6822  (void)attr; /* avoid potential warning */
6823  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6824  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6825  out_infos[0].req = &ia32_class_reg_req_xmm;
6826 
6827  verify_new_node(res);
6828  return optimize_node(res);
6829 }
6830 
6831 ir_node *new_bd_ia32_xLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
6832 {
6833  static arch_register_req_t const *in_reqs[] = {
6834  &ia32_class_reg_req_gp,
6835  &ia32_class_reg_req_gp,
6836  &arch_memory_requirement,
6837  };
6838 
6839  /* construct in array */
6840  ir_node *const in[] = {
6841  base,
6842  index,
6843  mem,
6844  };
6845 
6846  ir_graph *const irg = get_irn_irg(block);
6847  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xLoad, mode_T, 3, in);
6848 
6849  /* flags */
6850  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6851 
6852  /* init node attributes */
6853  int const n_res = 5;
6854  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6855  (void)attr; /* avoid potential warning */
6856  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6857  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6858  out_infos[0].req = &ia32_class_reg_req_xmm;
6859  out_infos[1].req = &arch_no_requirement;
6860  out_infos[2].req = &arch_memory_requirement;
6861  out_infos[3].req = &arch_exec_requirement;
6862  out_infos[4].req = &arch_exec_requirement;
6863 
6864  verify_new_node(res);
6865  return optimize_node(res);
6866 }
6867 
6868 ir_node *new_bd_ia32_xPzero(dbg_info *dbgi, ir_node *block, x86_insn_size_t size)
6869 {
6870  arch_register_req_t const **const in_reqs = NULL;
6871 
6872 
6873  ir_graph *const irg = get_irn_irg(block);
6874  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xPzero, ia32_mode_float64, 0, NULL);
6875 
6876  /* flags */
6877  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6878  irn_flags |= arch_irn_flag_rematerializable;
6879 
6880  /* init node attributes */
6881  int const n_res = 1;
6882  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6883  (void)attr; /* avoid potential warning */
6884  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6885  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6886  out_infos[0].req = &ia32_class_reg_req_xmm;
6887 
6888  verify_new_node(res);
6889  return optimize_node(res);
6890 }
6891 
6892 ir_node *new_bd_ia32_xStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
6893 {
6894  static arch_register_req_t const *in_reqs[] = {
6895  &ia32_class_reg_req_gp,
6896  &ia32_class_reg_req_gp,
6897  &arch_memory_requirement,
6898  &ia32_class_reg_req_xmm,
6899  };
6900 
6901  /* construct in array */
6902  ir_node *const in[] = {
6903  base,
6904  index,
6905  mem,
6906  val,
6907  };
6908 
6909  ir_graph *const irg = get_irn_irg(block);
6910  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xStore, mode_T, 4, in);
6911 
6912  /* flags */
6913  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6914 
6915  /* init node attributes */
6916  int const n_res = 3;
6917  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6918  (void)attr; /* avoid potential warning */
6919  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6920  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6921  out_infos[0].req = &arch_memory_requirement;
6922  out_infos[1].req = &arch_exec_requirement;
6923  out_infos[2].req = &arch_exec_requirement;
6924 
6925  verify_new_node(res);
6926  return optimize_node(res);
6927 }
6928 
6929 ir_node *new_bd_ia32_xZero(dbg_info *dbgi, ir_node *block, x86_insn_size_t size)
6930 {
6931  arch_register_req_t const **const in_reqs = NULL;
6932 
6933 
6934  ir_graph *const irg = get_irn_irg(block);
6935  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xZero, ia32_mode_float64, 0, NULL);
6936 
6937  /* flags */
6938  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6939  irn_flags |= arch_irn_flag_rematerializable;
6940 
6941  /* init node attributes */
6942  int const n_res = 1;
6943  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6944  (void)attr; /* avoid potential warning */
6945  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6946  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6947  out_infos[0].req = &ia32_class_reg_req_xmm;
6948 
6949  verify_new_node(res);
6950  return optimize_node(res);
6951 }
6952 
6953 ir_node *new_bd_ia32_xxLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, x86_insn_size_t size)
6954 {
6955  static arch_register_req_t const *in_reqs[] = {
6956  &ia32_class_reg_req_gp,
6957  &ia32_class_reg_req_gp,
6958  &arch_memory_requirement,
6959  };
6960 
6961  /* construct in array */
6962  ir_node *const in[] = {
6963  base,
6964  index,
6965  mem,
6966  };
6967 
6968  ir_graph *const irg = get_irn_irg(block);
6969  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xxLoad, mode_T, 3, in);
6970 
6971  /* flags */
6972  arch_irn_flags_t irn_flags = arch_irn_flags_none;
6973 
6974  /* init node attributes */
6975  int const n_res = 4;
6976  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
6977  (void)attr; /* avoid potential warning */
6978  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
6979  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
6980  out_infos[0].req = &ia32_class_reg_req_xmm;
6981  out_infos[1].req = &arch_memory_requirement;
6982  out_infos[2].req = &arch_exec_requirement;
6983  out_infos[3].req = &arch_exec_requirement;
6984 
6985  verify_new_node(res);
6986  return optimize_node(res);
6987 }
6988 
6989 ir_node *new_bd_ia32_xxStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, x86_insn_size_t size)
6990 {
6991  static arch_register_req_t const *in_reqs[] = {
6992  &ia32_class_reg_req_gp,
6993  &ia32_class_reg_req_gp,
6994  &arch_memory_requirement,
6995  &ia32_class_reg_req_xmm,
6996  };
6997 
6998  /* construct in array */
6999  ir_node *const in[] = {
7000  base,
7001  index,
7002  mem,
7003  val,
7004  };
7005 
7006  ir_graph *const irg = get_irn_irg(block);
7007  ir_node *const res = new_ir_node(dbgi, irg, block, op_ia32_xxStore, mode_T, 4, in);
7008 
7009  /* flags */
7010  arch_irn_flags_t irn_flags = arch_irn_flags_none;
7011 
7012  /* init node attributes */
7013  int const n_res = 3;
7014  ia32_attr_t *const attr = (ia32_attr_t*)get_irn_generic_attr(res);
7015  (void)attr; /* avoid potential warning */
7016  init_ia32_attributes(res, irn_flags, in_reqs, n_res, size);
7017  reg_out_info_t *const out_infos = be_get_info(res)->out_infos;
7018  out_infos[0].req = &arch_memory_requirement;
7019  out_infos[1].req = &arch_exec_requirement;
7020  out_infos[2].req = &arch_exec_requirement;
7021 
7022  verify_new_node(res);
7023  return optimize_node(res);
7024 }
7025 
7026 
7031 void ia32_create_opcodes(void)
7032 {
7033  ir_op *op;
7034  int cur_opcode = get_next_ir_opcodes(iro_ia32_last);
7035 
7036  ia32_opcode_start = cur_opcode;
7037  op = new_ir_op(cur_opcode + iro_ia32_Adc, "ia32_Adc", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7038  set_op_dump(op, ia32_dump_node);
7039  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7040  set_op_copy_attr(op, be_copy_attr);
7041  set_op_tag(op, ia32_op_tag);
7042  ia32_init_op(op, 1);
7043  op_ia32_Adc = op;
7044  op = new_ir_op(cur_opcode + iro_ia32_Add, "ia32_Add", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7045  set_op_dump(op, ia32_dump_node);
7046  set_op_attrs_equal(op, ia32_attrs_equal);
7047  set_op_copy_attr(op, be_copy_attr);
7048  set_op_tag(op, ia32_op_tag);
7049  ia32_init_op(op, 1);
7050  op_ia32_Add = op;
7051  op = new_ir_op(cur_opcode + iro_ia32_AddMem, "ia32_AddMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7052  set_op_dump(op, ia32_dump_node);
7053  set_op_attrs_equal(op, ia32_attrs_equal);
7054  set_op_copy_attr(op, be_copy_attr);
7055  set_op_tag(op, ia32_op_tag);
7056  ia32_init_op(op, 1);
7057  op_ia32_AddMem = op;
7058  op = new_ir_op(cur_opcode + iro_ia32_AddSP, "ia32_AddSP", op_pin_state_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7059  set_op_dump(op, ia32_dump_node);
7060  set_op_attrs_equal(op, ia32_attrs_equal);
7061  set_op_copy_attr(op, be_copy_attr);
7062  set_op_tag(op, ia32_op_tag);
7063  ia32_init_op(op, 1);
7064  op_ia32_AddSP = op;
7065  op = new_ir_op(cur_opcode + iro_ia32_Adds, "ia32_Adds", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7066  set_op_dump(op, ia32_dump_node);
7067  set_op_attrs_equal(op, ia32_attrs_equal);
7068  set_op_copy_attr(op, be_copy_attr);
7069  set_op_tag(op, ia32_op_tag);
7070  ia32_init_op(op, 4);
7071  op_ia32_Adds = op;
7072  op = new_ir_op(cur_opcode + iro_ia32_And, "ia32_And", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7073  set_op_dump(op, ia32_dump_node);
7074  set_op_attrs_equal(op, ia32_attrs_equal);
7075  set_op_copy_attr(op, be_copy_attr);
7076  set_op_tag(op, ia32_op_tag);
7077  ia32_init_op(op, 1);
7078  op_ia32_And = op;
7079  op = new_ir_op(cur_opcode + iro_ia32_AndMem, "ia32_AndMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7080  set_op_dump(op, ia32_dump_node);
7081  set_op_attrs_equal(op, ia32_attrs_equal);
7082  set_op_copy_attr(op, be_copy_attr);
7083  set_op_tag(op, ia32_op_tag);
7084  ia32_init_op(op, 1);
7085  op_ia32_AndMem = op;
7086  op = new_ir_op(cur_opcode + iro_ia32_Andnp, "ia32_Andnp", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7087  set_op_dump(op, ia32_dump_node);
7088  set_op_attrs_equal(op, ia32_attrs_equal);
7089  set_op_copy_attr(op, be_copy_attr);
7090  set_op_tag(op, ia32_op_tag);
7091  ia32_init_op(op, 3);
7092  op_ia32_Andnp = op;
7093  op = new_ir_op(cur_opcode + iro_ia32_Andp, "ia32_Andp", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7094  set_op_dump(op, ia32_dump_node);
7095  set_op_attrs_equal(op, ia32_attrs_equal);
7096  set_op_copy_attr(op, be_copy_attr);
7097  set_op_tag(op, ia32_op_tag);
7098  ia32_init_op(op, 3);
7099  op_ia32_Andp = op;
7100  op = new_ir_op(cur_opcode + iro_ia32_Breakpoint, "ia32_Breakpoint", op_pin_state_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7101  set_op_dump(op, ia32_dump_node);
7102  set_op_attrs_equal(op, ia32_attrs_equal);
7103  set_op_copy_attr(op, be_copy_attr);
7104  set_op_tag(op, ia32_op_tag);
7105  ia32_init_op(op, 0);
7106  op_ia32_Breakpoint = op;
7107  op = new_ir_op(cur_opcode + iro_ia32_Bsf, "ia32_Bsf", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7108  set_op_dump(op, ia32_dump_node);
7109  set_op_attrs_equal(op, ia32_attrs_equal);
7110  set_op_copy_attr(op, be_copy_attr);
7111  set_op_tag(op, ia32_op_tag);
7112  ia32_init_op(op, 1);
7113  op_ia32_Bsf = op;
7114  op = new_ir_op(cur_opcode + iro_ia32_Bsr, "ia32_Bsr", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7115  set_op_dump(op, ia32_dump_node);
7116  set_op_attrs_equal(op, ia32_attrs_equal);
7117  set_op_copy_attr(op, be_copy_attr);
7118  set_op_tag(op, ia32_op_tag);
7119  ia32_init_op(op, 1);
7120  op_ia32_Bsr = op;
7121  op = new_ir_op(cur_opcode + iro_ia32_Bswap, "ia32_Bswap", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7122  set_op_dump(op, ia32_dump_node);
7123  set_op_attrs_equal(op, ia32_attrs_equal);
7124  set_op_copy_attr(op, be_copy_attr);
7125  set_op_tag(op, ia32_op_tag);
7126  ia32_init_op(op, 1);
7127  op_ia32_Bswap = op;
7128  op = new_ir_op(cur_opcode + iro_ia32_Bswap16, "ia32_Bswap16", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7129  set_op_dump(op, ia32_dump_node);
7130  set_op_attrs_equal(op, ia32_attrs_equal);
7131  set_op_copy_attr(op, be_copy_attr);
7132  set_op_tag(op, ia32_op_tag);
7133  ia32_init_op(op, 1);
7134  op_ia32_Bswap16 = op;
7135  op = new_ir_op(cur_opcode + iro_ia32_Bt, "ia32_Bt", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7136  set_op_dump(op, ia32_dump_node);
7137  set_op_attrs_equal(op, ia32_attrs_equal);
7138  set_op_copy_attr(op, be_copy_attr);
7139  set_op_tag(op, ia32_op_tag);
7140  ia32_init_op(op, 1);
7141  op_ia32_Bt = op;
7142  op = new_ir_op(cur_opcode + iro_ia32_CMovcc, "ia32_CMovcc", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7143  set_op_dump(op, ia32_dump_node);
7144  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7145  set_op_copy_attr(op, be_copy_attr);
7146  set_op_tag(op, ia32_op_tag);
7147  ia32_init_op(op, 1);
7148  op_ia32_CMovcc = op;
7149  op = new_ir_op(cur_opcode + iro_ia32_Call, "ia32_Call", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_variable, -1, sizeof(ia32_call_attr_t));
7150  set_op_dump(op, ia32_dump_node);
7151  set_op_attrs_equal(op, ia32_call_attrs_equal);
7152  set_op_copy_attr(op, be_copy_attr);
7153  set_op_tag(op, ia32_op_tag);
7154  ia32_init_op(op, 4);
7155  op_ia32_Call = op;
7156  op = new_ir_op(cur_opcode + iro_ia32_ChangeCW, "ia32_ChangeCW", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_any, -1, sizeof(ia32_attr_t));
7157  set_op_dump(op, ia32_dump_node);
7158  set_op_attrs_equal(op, ia32_attrs_equal);
7159  set_op_copy_attr(op, be_copy_attr);
7160  set_op_tag(op, ia32_op_tag);
7161  ia32_init_op(op, 3);
7162  op_ia32_ChangeCW = op;
7163  op = new_ir_op(cur_opcode + iro_ia32_Cltd, "ia32_Cltd", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7164  set_op_dump(op, ia32_dump_node);
7165  set_op_attrs_equal(op, ia32_attrs_equal);
7166  set_op_copy_attr(op, be_copy_attr);
7167  set_op_tag(op, ia32_op_tag);
7168  ia32_init_op(op, 1);
7169  op_ia32_Cltd = op;
7170  op = new_ir_op(cur_opcode + iro_ia32_Cmc, "ia32_Cmc", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7171  set_op_dump(op, ia32_dump_node);
7172  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7173  set_op_copy_attr(op, be_copy_attr);
7174  set_op_tag(op, ia32_op_tag);
7175  ia32_init_op(op, 1);
7176  op_ia32_Cmc = op;
7177  op = new_ir_op(cur_opcode + iro_ia32_Cmp, "ia32_Cmp", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7178  set_op_dump(op, ia32_dump_node);
7179  set_op_attrs_equal(op, ia32_attrs_equal);
7180  set_op_copy_attr(op, be_copy_attr);
7181  set_op_tag(op, ia32_op_tag);
7182  ia32_init_op(op, 1);
7183  op_ia32_Cmp = op;
7184  op = new_ir_op(cur_opcode + iro_ia32_CmpXChgMem, "ia32_CmpXChgMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7185  set_op_dump(op, ia32_dump_node);
7186  set_op_attrs_equal(op, ia32_attrs_equal);
7187  set_op_copy_attr(op, be_copy_attr);
7188  set_op_tag(op, ia32_op_tag);
7189  ia32_init_op(op, 2);
7190  op_ia32_CmpXChgMem = op;
7191  op = new_ir_op(cur_opcode + iro_ia32_Const, "ia32_Const", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_immediate_attr_t));
7192  set_op_dump(op, ia32_dump_node);
7193  set_op_attrs_equal(op, ia32_immediate_attrs_equal);
7194  set_op_copy_attr(op, be_copy_attr);
7195  set_op_tag(op, ia32_op_tag);
7196  ia32_init_op(op, 1);
7197  op_ia32_Const = op;
7198  op = new_ir_op(cur_opcode + iro_ia32_Conv_FP2FP, "ia32_Conv_FP2FP", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7199  set_op_dump(op, ia32_dump_node);
7200  set_op_attrs_equal(op, ia32_attrs_equal);
7201  set_op_copy_attr(op, be_copy_attr);
7202  set_op_tag(op, ia32_op_tag);
7203  ia32_init_op(op, 8);
7204  op_ia32_Conv_FP2FP = op;
7205  op = new_ir_op(cur_opcode + iro_ia32_Conv_FP2I, "ia32_Conv_FP2I", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7206  set_op_dump(op, ia32_dump_node);
7207  set_op_attrs_equal(op, ia32_attrs_equal);
7208  set_op_copy_attr(op, be_copy_attr);
7209  set_op_tag(op, ia32_op_tag);
7210  ia32_init_op(op, 10);
7211  op_ia32_Conv_FP2I = op;
7212  op = new_ir_op(cur_opcode + iro_ia32_Conv_I2FP, "ia32_Conv_I2FP", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7213  set_op_dump(op, ia32_dump_node);
7214  set_op_attrs_equal(op, ia32_attrs_equal);
7215  set_op_copy_attr(op, be_copy_attr);
7216  set_op_tag(op, ia32_op_tag);
7217  ia32_init_op(op, 10);
7218  op_ia32_Conv_I2FP = op;
7219  op = new_ir_op(cur_opcode + iro_ia32_Conv_I2I, "ia32_Conv_I2I", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_attr_t));
7220  set_op_dump(op, ia32_dump_node);
7221  set_op_attrs_equal(op, ia32_attrs_equal);
7222  set_op_copy_attr(op, be_copy_attr);
7223  ir_op_set_memory_index(op, n_ia32_Conv_I2I_mem);
7224  ir_op_set_fragile_indices(op, pn_ia32_Conv_I2I_X_regular, pn_ia32_Conv_I2I_X_except);
7225  set_op_tag(op, ia32_op_tag);
7226  ia32_init_op(op, 1);
7227  op_ia32_Conv_I2I = op;
7228  op = new_ir_op(cur_opcode + iro_ia32_CopyB, "ia32_CopyB", op_pin_state_floats, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_copyb_attr_t));
7229  set_op_dump(op, ia32_dump_node);
7230  set_op_attrs_equal(op, ia32_copyb_attrs_equal);
7231  set_op_copy_attr(op, be_copy_attr);
7232  set_op_tag(op, ia32_op_tag);
7233  ia32_init_op(op, 250);
7234  op_ia32_CopyB = op;
7235  op = new_ir_op(cur_opcode + iro_ia32_CopyB_i, "ia32_CopyB_i", op_pin_state_floats, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_copyb_attr_t));
7236  set_op_dump(op, ia32_dump_node);
7237  set_op_attrs_equal(op, ia32_copyb_attrs_equal);
7238  set_op_copy_attr(op, be_copy_attr);
7239  set_op_tag(op, ia32_op_tag);
7240  ia32_init_op(op, 3);
7241  op_ia32_CopyB_i = op;
7242  op = new_ir_op(cur_opcode + iro_ia32_CopyEbpEsp, "ia32_CopyEbpEsp", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7243  set_op_dump(op, ia32_dump_node);
7244  set_op_attrs_equal(op, ia32_attrs_equal);
7245  set_op_copy_attr(op, be_copy_attr);
7246  set_op_tag(op, ia32_op_tag);
7247  ia32_init_op(op, 1);
7248  op_ia32_CopyEbpEsp = op;
7249  op = new_ir_op(cur_opcode + iro_ia32_CvtSI2SD, "ia32_CvtSI2SD", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7250  set_op_dump(op, ia32_dump_node);
7251  set_op_attrs_equal(op, ia32_attrs_equal);
7252  set_op_copy_attr(op, be_copy_attr);
7253  set_op_tag(op, ia32_op_tag);
7254  ia32_init_op(op, 2);
7255  op_ia32_CvtSI2SD = op;
7256  op = new_ir_op(cur_opcode + iro_ia32_CvtSI2SS, "ia32_CvtSI2SS", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7257  set_op_dump(op, ia32_dump_node);
7258  set_op_attrs_equal(op, ia32_attrs_equal);
7259  set_op_copy_attr(op, be_copy_attr);
7260  set_op_tag(op, ia32_op_tag);
7261  ia32_init_op(op, 2);
7262  op_ia32_CvtSI2SS = op;
7263  op = new_ir_op(cur_opcode + iro_ia32_Cwtl, "ia32_Cwtl", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7264  set_op_dump(op, ia32_dump_node);
7265  set_op_attrs_equal(op, ia32_attrs_equal);
7266  set_op_copy_attr(op, be_copy_attr);
7267  set_op_tag(op, ia32_op_tag);
7268  ia32_init_op(op, 1);
7269  op_ia32_Cwtl = op;
7270  op = new_ir_op(cur_opcode + iro_ia32_Dec, "ia32_Dec", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7271  set_op_dump(op, ia32_dump_node);
7272  set_op_attrs_equal(op, ia32_attrs_equal);
7273  set_op_copy_attr(op, be_copy_attr);
7274  set_op_tag(op, ia32_op_tag);
7275  ia32_init_op(op, 1);
7276  op_ia32_Dec = op;
7277  op = new_ir_op(cur_opcode + iro_ia32_DecMem, "ia32_DecMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7278  set_op_dump(op, ia32_dump_node);
7279  set_op_attrs_equal(op, ia32_attrs_equal);
7280  set_op_copy_attr(op, be_copy_attr);
7281  set_op_tag(op, ia32_op_tag);
7282  ia32_init_op(op, 1);
7283  op_ia32_DecMem = op;
7284  op = new_ir_op(cur_opcode + iro_ia32_Div, "ia32_Div", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7285  set_op_dump(op, ia32_dump_node);
7286  set_op_attrs_equal(op, ia32_attrs_equal);
7287  set_op_copy_attr(op, be_copy_attr);
7288  ir_op_set_memory_index(op, n_ia32_Div_mem);
7289  ir_op_set_fragile_indices(op, pn_ia32_Div_X_regular, pn_ia32_Div_X_except);
7290  set_op_tag(op, ia32_op_tag);
7291  ia32_init_op(op, 25);
7292  op_ia32_Div = op;
7293  op = new_ir_op(cur_opcode + iro_ia32_Divs, "ia32_Divs", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7294  set_op_dump(op, ia32_dump_node);
7295  set_op_attrs_equal(op, ia32_attrs_equal);
7296  set_op_copy_attr(op, be_copy_attr);
7297  set_op_tag(op, ia32_op_tag);
7298  ia32_init_op(op, 16);
7299  op_ia32_Divs = op;
7300  op = new_ir_op(cur_opcode + iro_ia32_Enter, "ia32_Enter", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7301  set_op_dump(op, ia32_dump_node);
7302  set_op_attrs_equal(op, ia32_attrs_equal);
7303  set_op_copy_attr(op, be_copy_attr);
7304  set_op_tag(op, ia32_op_tag);
7305  ia32_init_op(op, 15);
7306  op_ia32_Enter = op;
7307  op = new_ir_op(cur_opcode + iro_ia32_FldCW, "ia32_FldCW", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7308  set_op_dump(op, ia32_dump_node);
7309  set_op_attrs_equal(op, ia32_attrs_equal);
7310  set_op_copy_attr(op, be_copy_attr);
7311  set_op_tag(op, ia32_op_tag);
7312  ia32_init_op(op, 5);
7313  op_ia32_FldCW = op;
7314  op = new_ir_op(cur_opcode + iro_ia32_FnstCW, "ia32_FnstCW", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7315  set_op_dump(op, ia32_dump_node);
7316  set_op_attrs_equal(op, ia32_attrs_equal);
7317  set_op_copy_attr(op, be_copy_attr);
7318  set_op_tag(op, ia32_op_tag);
7319  ia32_init_op(op, 5);
7320  op_ia32_FnstCW = op;
7321  op = new_ir_op(cur_opcode + iro_ia32_FnstCWNOP, "ia32_FnstCWNOP", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7322  set_op_dump(op, ia32_dump_node);
7323  set_op_attrs_equal(op, ia32_attrs_equal);
7324  set_op_copy_attr(op, be_copy_attr);
7325  set_op_tag(op, ia32_op_tag);
7326  ia32_init_op(op, 0);
7327  op_ia32_FnstCWNOP = op;
7328  op = new_ir_op(cur_opcode + iro_ia32_FtstFnstsw, "ia32_FtstFnstsw", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7329  set_op_dump(op, ia32_dump_node);
7330  set_op_attrs_equal(op, ia32_attrs_equal);
7331  set_op_copy_attr(op, be_copy_attr);
7332  set_op_tag(op, ia32_op_tag);
7333  ia32_init_op(op, 3);
7334  op_ia32_FtstFnstsw = op;
7335  op = new_ir_op(cur_opcode + iro_ia32_FucomFnstsw, "ia32_FucomFnstsw", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7336  set_op_dump(op, ia32_dump_node);
7337  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7338  set_op_copy_attr(op, be_copy_attr);
7339  set_op_tag(op, ia32_op_tag);
7340  ia32_init_op(op, 3);
7341  op_ia32_FucomFnstsw = op;
7342  op = new_ir_op(cur_opcode + iro_ia32_Fucomi, "ia32_Fucomi", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7343  set_op_dump(op, ia32_dump_node);
7344  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7345  set_op_copy_attr(op, be_copy_attr);
7346  set_op_tag(op, ia32_op_tag);
7347  ia32_init_op(op, 3);
7348  op_ia32_Fucomi = op;
7349  op = new_ir_op(cur_opcode + iro_ia32_FucomppFnstsw, "ia32_FucomppFnstsw", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7350  set_op_dump(op, ia32_dump_node);
7351  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7352  set_op_copy_attr(op, be_copy_attr);
7353  set_op_tag(op, ia32_op_tag);
7354  ia32_init_op(op, 3);
7355  op_ia32_FucomppFnstsw = op;
7356  op = new_ir_op(cur_opcode + iro_ia32_GetEIP, "ia32_GetEIP", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
7357  set_op_dump(op, ia32_dump_node);
7358  set_op_attrs_equal(op, ia32_attrs_equal);
7359  set_op_copy_attr(op, be_copy_attr);
7360  set_op_tag(op, ia32_op_tag);
7361  ia32_init_op(op, 5);
7362  op_ia32_GetEIP = op;
7363  op = new_ir_op(cur_opcode + iro_ia32_IDiv, "ia32_IDiv", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7364  set_op_dump(op, ia32_dump_node);
7365  set_op_attrs_equal(op, ia32_attrs_equal);
7366  set_op_copy_attr(op, be_copy_attr);
7367  ir_op_set_memory_index(op, n_ia32_IDiv_mem);
7368  ir_op_set_fragile_indices(op, pn_ia32_IDiv_X_regular, pn_ia32_IDiv_X_except);
7369  set_op_tag(op, ia32_op_tag);
7370  ia32_init_op(op, 25);
7371  op_ia32_IDiv = op;
7372  op = new_ir_op(cur_opcode + iro_ia32_IJmp, "ia32_IJmp", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_unknown_jump, oparity_any, -1, sizeof(ia32_attr_t));
7373  set_op_dump(op, ia32_dump_node);
7374  set_op_attrs_equal(op, ia32_attrs_equal);
7375  set_op_copy_attr(op, be_copy_attr);
7376  set_op_tag(op, ia32_op_tag);
7377  ia32_init_op(op, 1);
7378  op_ia32_IJmp = op;
7379  op = new_ir_op(cur_opcode + iro_ia32_IMul, "ia32_IMul", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7380  set_op_dump(op, ia32_dump_node);
7381  set_op_attrs_equal(op, ia32_attrs_equal);
7382  set_op_copy_attr(op, be_copy_attr);
7383  set_op_tag(op, ia32_op_tag);
7384  ia32_init_op(op, 5);
7385  op_ia32_IMul = op;
7386  op = new_ir_op(cur_opcode + iro_ia32_IMul1OP, "ia32_IMul1OP", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7387  set_op_dump(op, ia32_dump_node);
7388  set_op_attrs_equal(op, ia32_attrs_equal);
7389  set_op_copy_attr(op, be_copy_attr);
7390  set_op_tag(op, ia32_op_tag);
7391  ia32_init_op(op, 5);
7392  op_ia32_IMul1OP = op;
7393  op = new_ir_op(cur_opcode + iro_ia32_IMulImm, "ia32_IMulImm", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7394  set_op_dump(op, ia32_dump_node);
7395  set_op_attrs_equal(op, ia32_attrs_equal);
7396  set_op_copy_attr(op, be_copy_attr);
7397  set_op_tag(op, ia32_op_tag);
7398  ia32_init_op(op, 5);
7399  op_ia32_IMulImm = op;
7400  op = new_ir_op(cur_opcode + iro_ia32_Immediate, "ia32_Immediate", op_pin_state_pinned, irop_flag_constlike, oparity_any, -1, sizeof(ia32_immediate_attr_t));
7401  set_op_dump(op, ia32_dump_node);
7402  set_op_attrs_equal(op, ia32_immediate_attrs_equal);
7403  set_op_copy_attr(op, be_copy_attr);
7404  set_op_hash(op, ia32_hash_Immediate);
7405  set_op_tag(op, ia32_op_tag);
7406  ia32_init_op(op, 0);
7407  op_ia32_Immediate = op;
7408  op = new_ir_op(cur_opcode + iro_ia32_Inc, "ia32_Inc", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7409  set_op_dump(op, ia32_dump_node);
7410  set_op_attrs_equal(op, ia32_attrs_equal);
7411  set_op_copy_attr(op, be_copy_attr);
7412  set_op_tag(op, ia32_op_tag);
7413  ia32_init_op(op, 1);
7414  op_ia32_Inc = op;
7415  op = new_ir_op(cur_opcode + iro_ia32_IncMem, "ia32_IncMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7416  set_op_dump(op, ia32_dump_node);
7417  set_op_attrs_equal(op, ia32_attrs_equal);
7418  set_op_copy_attr(op, be_copy_attr);
7419  set_op_tag(op, ia32_op_tag);
7420  ia32_init_op(op, 1);
7421  op_ia32_IncMem = op;
7422  op = new_ir_op(cur_opcode + iro_ia32_Inport, "ia32_Inport", op_pin_state_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7423  set_op_dump(op, ia32_dump_node);
7424  set_op_attrs_equal(op, ia32_attrs_equal);
7425  set_op_copy_attr(op, be_copy_attr);
7426  set_op_tag(op, ia32_op_tag);
7427  ia32_init_op(op, 1);
7428  op_ia32_Inport = op;
7429  op = new_ir_op(cur_opcode + iro_ia32_Jcc, "ia32_Jcc", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_forking, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7430  set_op_dump(op, ia32_dump_node);
7431  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7432  set_op_copy_attr(op, be_copy_attr);
7433  set_op_tag(op, ia32_op_tag);
7434  ia32_init_op(op, 2);
7435  op_ia32_Jcc = op;
7436  op = new_ir_op(cur_opcode + iro_ia32_Jmp, "ia32_Jmp", op_pin_state_pinned, irop_flag_cfopcode, oparity_any, -1, sizeof(ia32_attr_t));
7437  set_op_dump(op, ia32_dump_node);
7438  set_op_attrs_equal(op, ia32_attrs_equal);
7439  set_op_copy_attr(op, be_copy_attr);
7440  set_op_tag(op, ia32_op_tag);
7441  ia32_init_op(op, 1);
7442  op_ia32_Jmp = op;
7443  op = new_ir_op(cur_opcode + iro_ia32_LdTls, "ia32_LdTls", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
7444  set_op_dump(op, ia32_dump_node);
7445  set_op_attrs_equal(op, ia32_attrs_equal);
7446  set_op_copy_attr(op, be_copy_attr);
7447  set_op_tag(op, ia32_op_tag);
7448  ia32_init_op(op, 1);
7449  op_ia32_LdTls = op;
7450  op = new_ir_op(cur_opcode + iro_ia32_Lea, "ia32_Lea", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7451  set_op_dump(op, ia32_dump_node);
7452  set_op_attrs_equal(op, ia32_attrs_equal);
7453  set_op_copy_attr(op, be_copy_attr);
7454  set_op_tag(op, ia32_op_tag);
7455  ia32_init_op(op, 2);
7456  op_ia32_Lea = op;
7457  op = new_ir_op(cur_opcode + iro_ia32_Leave, "ia32_Leave", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7458  set_op_dump(op, ia32_dump_node);
7459  set_op_attrs_equal(op, ia32_attrs_equal);
7460  set_op_copy_attr(op, be_copy_attr);
7461  set_op_tag(op, ia32_op_tag);
7462  ia32_init_op(op, 3);
7463  op_ia32_Leave = op;
7464  op = new_ir_op(cur_opcode + iro_ia32_Load, "ia32_Load", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_attr_t));
7465  set_op_dump(op, ia32_dump_node);
7466  set_op_attrs_equal(op, ia32_attrs_equal);
7467  set_op_copy_attr(op, be_copy_attr);
7468  ir_op_set_memory_index(op, n_ia32_Load_mem);
7469  ir_op_set_fragile_indices(op, pn_ia32_Load_X_regular, pn_ia32_Load_X_except);
7470  set_op_tag(op, ia32_op_tag);
7471  ia32_init_op(op, 0);
7472  op_ia32_Load = op;
7473  op = new_ir_op(cur_opcode + iro_ia32_Maxs, "ia32_Maxs", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7474  set_op_dump(op, ia32_dump_node);
7475  set_op_attrs_equal(op, ia32_attrs_equal);
7476  set_op_copy_attr(op, be_copy_attr);
7477  set_op_tag(op, ia32_op_tag);
7478  ia32_init_op(op, 2);
7479  op_ia32_Maxs = op;
7480  op = new_ir_op(cur_opcode + iro_ia32_Mins, "ia32_Mins", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7481  set_op_dump(op, ia32_dump_node);
7482  set_op_attrs_equal(op, ia32_attrs_equal);
7483  set_op_copy_attr(op, be_copy_attr);
7484  set_op_tag(op, ia32_op_tag);
7485  ia32_init_op(op, 2);
7486  op_ia32_Mins = op;
7487  op = new_ir_op(cur_opcode + iro_ia32_Minus64, "ia32_Minus64", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7488  set_op_dump(op, ia32_dump_node);
7489  set_op_attrs_equal(op, ia32_attrs_equal);
7490  set_op_copy_attr(op, be_copy_attr);
7491  set_op_tag(op, ia32_op_tag);
7492  ia32_init_op(op, 3);
7493  op_ia32_Minus64 = op;
7494  op = new_ir_op(cur_opcode + iro_ia32_Movd, "ia32_Movd", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7495  set_op_dump(op, ia32_dump_node);
7496  set_op_attrs_equal(op, ia32_attrs_equal);
7497  set_op_copy_attr(op, be_copy_attr);
7498  set_op_tag(op, ia32_op_tag);
7499  ia32_init_op(op, 1);
7500  op_ia32_Movd = op;
7501  op = new_ir_op(cur_opcode + iro_ia32_Mul, "ia32_Mul", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7502  set_op_dump(op, ia32_dump_node);
7503  set_op_attrs_equal(op, ia32_attrs_equal);
7504  set_op_copy_attr(op, be_copy_attr);
7505  set_op_tag(op, ia32_op_tag);
7506  ia32_init_op(op, 10);
7507  op_ia32_Mul = op;
7508  op = new_ir_op(cur_opcode + iro_ia32_Muls, "ia32_Muls", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7509  set_op_dump(op, ia32_dump_node);
7510  set_op_attrs_equal(op, ia32_attrs_equal);
7511  set_op_copy_attr(op, be_copy_attr);
7512  set_op_tag(op, ia32_op_tag);
7513  ia32_init_op(op, 4);
7514  op_ia32_Muls = op;
7515  op = new_ir_op(cur_opcode + iro_ia32_Neg, "ia32_Neg", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7516  set_op_dump(op, ia32_dump_node);
7517  set_op_attrs_equal(op, ia32_attrs_equal);
7518  set_op_copy_attr(op, be_copy_attr);
7519  set_op_tag(op, ia32_op_tag);
7520  ia32_init_op(op, 1);
7521  op_ia32_Neg = op;
7522  op = new_ir_op(cur_opcode + iro_ia32_NegMem, "ia32_NegMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7523  set_op_dump(op, ia32_dump_node);
7524  set_op_attrs_equal(op, ia32_attrs_equal);
7525  set_op_copy_attr(op, be_copy_attr);
7526  set_op_tag(op, ia32_op_tag);
7527  ia32_init_op(op, 1);
7528  op_ia32_NegMem = op;
7529  op = new_ir_op(cur_opcode + iro_ia32_NoReg_FP, "ia32_NoReg_FP", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_any, -1, sizeof(ia32_attr_t));
7530  set_op_dump(op, ia32_dump_node);
7531  set_op_attrs_equal(op, ia32_attrs_equal);
7532  set_op_copy_attr(op, be_copy_attr);
7533  set_op_tag(op, ia32_op_tag);
7534  ia32_init_op(op, 0);
7535  op_ia32_NoReg_FP = op;
7536  op = new_ir_op(cur_opcode + iro_ia32_NoReg_GP, "ia32_NoReg_GP", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_any, -1, sizeof(ia32_attr_t));
7537  set_op_dump(op, ia32_dump_node);
7538  set_op_attrs_equal(op, ia32_attrs_equal);
7539  set_op_copy_attr(op, be_copy_attr);
7540  set_op_tag(op, ia32_op_tag);
7541  ia32_init_op(op, 0);
7542  op_ia32_NoReg_GP = op;
7543  op = new_ir_op(cur_opcode + iro_ia32_NoReg_XMM, "ia32_NoReg_XMM", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_any, -1, sizeof(ia32_attr_t));
7544  set_op_dump(op, ia32_dump_node);
7545  set_op_attrs_equal(op, ia32_attrs_equal);
7546  set_op_copy_attr(op, be_copy_attr);
7547  set_op_tag(op, ia32_op_tag);
7548  ia32_init_op(op, 0);
7549  op_ia32_NoReg_XMM = op;
7550  op = new_ir_op(cur_opcode + iro_ia32_Not, "ia32_Not", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7551  set_op_dump(op, ia32_dump_node);
7552  set_op_attrs_equal(op, ia32_attrs_equal);
7553  set_op_copy_attr(op, be_copy_attr);
7554  set_op_tag(op, ia32_op_tag);
7555  ia32_init_op(op, 1);
7556  op_ia32_Not = op;
7557  op = new_ir_op(cur_opcode + iro_ia32_NotMem, "ia32_NotMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7558  set_op_dump(op, ia32_dump_node);
7559  set_op_attrs_equal(op, ia32_attrs_equal);
7560  set_op_copy_attr(op, be_copy_attr);
7561  set_op_tag(op, ia32_op_tag);
7562  ia32_init_op(op, 1);
7563  op_ia32_NotMem = op;
7564  op = new_ir_op(cur_opcode + iro_ia32_Or, "ia32_Or", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7565  set_op_dump(op, ia32_dump_node);
7566  set_op_attrs_equal(op, ia32_attrs_equal);
7567  set_op_copy_attr(op, be_copy_attr);
7568  set_op_tag(op, ia32_op_tag);
7569  ia32_init_op(op, 1);
7570  op_ia32_Or = op;
7571  op = new_ir_op(cur_opcode + iro_ia32_OrMem, "ia32_OrMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7572  set_op_dump(op, ia32_dump_node);
7573  set_op_attrs_equal(op, ia32_attrs_equal);
7574  set_op_copy_attr(op, be_copy_attr);
7575  set_op_tag(op, ia32_op_tag);
7576  ia32_init_op(op, 1);
7577  op_ia32_OrMem = op;
7578  op = new_ir_op(cur_opcode + iro_ia32_Orp, "ia32_Orp", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7579  set_op_dump(op, ia32_dump_node);
7580  set_op_attrs_equal(op, ia32_attrs_equal);
7581  set_op_copy_attr(op, be_copy_attr);
7582  set_op_tag(op, ia32_op_tag);
7583  ia32_init_op(op, 3);
7584  op_ia32_Orp = op;
7585  op = new_ir_op(cur_opcode + iro_ia32_Outport, "ia32_Outport", op_pin_state_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7586  set_op_dump(op, ia32_dump_node);
7587  set_op_attrs_equal(op, ia32_attrs_equal);
7588  set_op_copy_attr(op, be_copy_attr);
7589  set_op_tag(op, ia32_op_tag);
7590  ia32_init_op(op, 1);
7591  op_ia32_Outport = op;
7592  op = new_ir_op(cur_opcode + iro_ia32_Pop, "ia32_Pop", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7593  set_op_dump(op, ia32_dump_node);
7594  set_op_attrs_equal(op, ia32_attrs_equal);
7595  set_op_copy_attr(op, be_copy_attr);
7596  set_op_tag(op, ia32_op_tag);
7597  ia32_init_op(op, 3);
7598  op_ia32_Pop = op;
7599  op = new_ir_op(cur_opcode + iro_ia32_PopMem, "ia32_PopMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7600  set_op_dump(op, ia32_dump_node);
7601  set_op_attrs_equal(op, ia32_attrs_equal);
7602  set_op_copy_attr(op, be_copy_attr);
7603  set_op_tag(op, ia32_op_tag);
7604  ia32_init_op(op, 3);
7605  op_ia32_PopMem = op;
7606  op = new_ir_op(cur_opcode + iro_ia32_Popcnt, "ia32_Popcnt", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7607  set_op_dump(op, ia32_dump_node);
7608  set_op_attrs_equal(op, ia32_attrs_equal);
7609  set_op_copy_attr(op, be_copy_attr);
7610  set_op_tag(op, ia32_op_tag);
7611  ia32_init_op(op, 1);
7612  op_ia32_Popcnt = op;
7613  op = new_ir_op(cur_opcode + iro_ia32_Prefetch, "ia32_Prefetch", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7614  set_op_dump(op, ia32_dump_node);
7615  set_op_attrs_equal(op, ia32_attrs_equal);
7616  set_op_copy_attr(op, be_copy_attr);
7617  set_op_tag(op, ia32_op_tag);
7618  ia32_init_op(op, 0);
7619  op_ia32_Prefetch = op;
7620  op = new_ir_op(cur_opcode + iro_ia32_PrefetchNTA, "ia32_PrefetchNTA", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7621  set_op_dump(op, ia32_dump_node);
7622  set_op_attrs_equal(op, ia32_attrs_equal);
7623  set_op_copy_attr(op, be_copy_attr);
7624  set_op_tag(op, ia32_op_tag);
7625  ia32_init_op(op, 0);
7626  op_ia32_PrefetchNTA = op;
7627  op = new_ir_op(cur_opcode + iro_ia32_PrefetchT0, "ia32_PrefetchT0", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7628  set_op_dump(op, ia32_dump_node);
7629  set_op_attrs_equal(op, ia32_attrs_equal);
7630  set_op_copy_attr(op, be_copy_attr);
7631  set_op_tag(op, ia32_op_tag);
7632  ia32_init_op(op, 0);
7633  op_ia32_PrefetchT0 = op;
7634  op = new_ir_op(cur_opcode + iro_ia32_PrefetchT1, "ia32_PrefetchT1", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7635  set_op_dump(op, ia32_dump_node);
7636  set_op_attrs_equal(op, ia32_attrs_equal);
7637  set_op_copy_attr(op, be_copy_attr);
7638  set_op_tag(op, ia32_op_tag);
7639  ia32_init_op(op, 0);
7640  op_ia32_PrefetchT1 = op;
7641  op = new_ir_op(cur_opcode + iro_ia32_PrefetchT2, "ia32_PrefetchT2", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7642  set_op_dump(op, ia32_dump_node);
7643  set_op_attrs_equal(op, ia32_attrs_equal);
7644  set_op_copy_attr(op, be_copy_attr);
7645  set_op_tag(op, ia32_op_tag);
7646  ia32_init_op(op, 0);
7647  op_ia32_PrefetchT2 = op;
7648  op = new_ir_op(cur_opcode + iro_ia32_PrefetchW, "ia32_PrefetchW", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_any, -1, sizeof(ia32_attr_t));
7649  set_op_dump(op, ia32_dump_node);
7650  set_op_attrs_equal(op, ia32_attrs_equal);
7651  set_op_copy_attr(op, be_copy_attr);
7652  set_op_tag(op, ia32_op_tag);
7653  ia32_init_op(op, 0);
7654  op_ia32_PrefetchW = op;
7655  op = new_ir_op(cur_opcode + iro_ia32_Pslld, "ia32_Pslld", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7656  set_op_dump(op, ia32_dump_node);
7657  set_op_attrs_equal(op, ia32_attrs_equal);
7658  set_op_copy_attr(op, be_copy_attr);
7659  set_op_tag(op, ia32_op_tag);
7660  ia32_init_op(op, 3);
7661  op_ia32_Pslld = op;
7662  op = new_ir_op(cur_opcode + iro_ia32_Psllq, "ia32_Psllq", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7663  set_op_dump(op, ia32_dump_node);
7664  set_op_attrs_equal(op, ia32_attrs_equal);
7665  set_op_copy_attr(op, be_copy_attr);
7666  set_op_tag(op, ia32_op_tag);
7667  ia32_init_op(op, 3);
7668  op_ia32_Psllq = op;
7669  op = new_ir_op(cur_opcode + iro_ia32_Psrld, "ia32_Psrld", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7670  set_op_dump(op, ia32_dump_node);
7671  set_op_attrs_equal(op, ia32_attrs_equal);
7672  set_op_copy_attr(op, be_copy_attr);
7673  set_op_tag(op, ia32_op_tag);
7674  ia32_init_op(op, 1);
7675  op_ia32_Psrld = op;
7676  op = new_ir_op(cur_opcode + iro_ia32_Push, "ia32_Push", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7677  set_op_dump(op, ia32_dump_node);
7678  set_op_attrs_equal(op, ia32_attrs_equal);
7679  set_op_copy_attr(op, be_copy_attr);
7680  set_op_tag(op, ia32_op_tag);
7681  ia32_init_op(op, 2);
7682  op_ia32_Push = op;
7683  op = new_ir_op(cur_opcode + iro_ia32_PushEax, "ia32_PushEax", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7684  set_op_dump(op, ia32_dump_node);
7685  set_op_attrs_equal(op, ia32_attrs_equal);
7686  set_op_copy_attr(op, be_copy_attr);
7687  set_op_tag(op, ia32_op_tag);
7688  ia32_init_op(op, 2);
7689  op_ia32_PushEax = op;
7690  op = new_ir_op(cur_opcode + iro_ia32_Return, "ia32_Return", op_pin_state_pinned, irop_flag_cfopcode, oparity_variable, -1, sizeof(ia32_return_attr_t));
7691  set_op_dump(op, ia32_dump_node);
7692  set_op_attrs_equal(op, ia32_return_attrs_equal);
7693  set_op_copy_attr(op, be_copy_attr);
7694  set_op_tag(op, ia32_op_tag);
7695  ia32_init_op(op, 0);
7696  op_ia32_Return = op;
7697  op = new_ir_op(cur_opcode + iro_ia32_Rol, "ia32_Rol", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7698  set_op_dump(op, ia32_dump_node);
7699  set_op_attrs_equal(op, ia32_attrs_equal);
7700  set_op_copy_attr(op, be_copy_attr);
7701  set_op_tag(op, ia32_op_tag);
7702  ia32_init_op(op, 1);
7703  op_ia32_Rol = op;
7704  op = new_ir_op(cur_opcode + iro_ia32_RolMem, "ia32_RolMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7705  set_op_dump(op, ia32_dump_node);
7706  set_op_attrs_equal(op, ia32_attrs_equal);
7707  set_op_copy_attr(op, be_copy_attr);
7708  set_op_tag(op, ia32_op_tag);
7709  ia32_init_op(op, 1);
7710  op_ia32_RolMem = op;
7711  op = new_ir_op(cur_opcode + iro_ia32_Ror, "ia32_Ror", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7712  set_op_dump(op, ia32_dump_node);
7713  set_op_attrs_equal(op, ia32_attrs_equal);
7714  set_op_copy_attr(op, be_copy_attr);
7715  set_op_tag(op, ia32_op_tag);
7716  ia32_init_op(op, 1);
7717  op_ia32_Ror = op;
7718  op = new_ir_op(cur_opcode + iro_ia32_RorMem, "ia32_RorMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7719  set_op_dump(op, ia32_dump_node);
7720  set_op_attrs_equal(op, ia32_attrs_equal);
7721  set_op_copy_attr(op, be_copy_attr);
7722  set_op_tag(op, ia32_op_tag);
7723  ia32_init_op(op, 1);
7724  op_ia32_RorMem = op;
7725  op = new_ir_op(cur_opcode + iro_ia32_Sahf, "ia32_Sahf", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7726  set_op_dump(op, ia32_dump_node);
7727  set_op_attrs_equal(op, ia32_attrs_equal);
7728  set_op_copy_attr(op, be_copy_attr);
7729  set_op_tag(op, ia32_op_tag);
7730  ia32_init_op(op, 1);
7731  op_ia32_Sahf = op;
7732  op = new_ir_op(cur_opcode + iro_ia32_Sar, "ia32_Sar", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7733  set_op_dump(op, ia32_dump_node);
7734  set_op_attrs_equal(op, ia32_attrs_equal);
7735  set_op_copy_attr(op, be_copy_attr);
7736  set_op_tag(op, ia32_op_tag);
7737  ia32_init_op(op, 1);
7738  op_ia32_Sar = op;
7739  op = new_ir_op(cur_opcode + iro_ia32_SarMem, "ia32_SarMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7740  set_op_dump(op, ia32_dump_node);
7741  set_op_attrs_equal(op, ia32_attrs_equal);
7742  set_op_copy_attr(op, be_copy_attr);
7743  set_op_tag(op, ia32_op_tag);
7744  ia32_init_op(op, 1);
7745  op_ia32_SarMem = op;
7746  op = new_ir_op(cur_opcode + iro_ia32_Sbb, "ia32_Sbb", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7747  set_op_dump(op, ia32_dump_node);
7748  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7749  set_op_copy_attr(op, be_copy_attr);
7750  set_op_tag(op, ia32_op_tag);
7751  ia32_init_op(op, 1);
7752  op_ia32_Sbb = op;
7753  op = new_ir_op(cur_opcode + iro_ia32_Sbb0, "ia32_Sbb0", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7754  set_op_dump(op, ia32_dump_node);
7755  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7756  set_op_copy_attr(op, be_copy_attr);
7757  set_op_tag(op, ia32_op_tag);
7758  ia32_init_op(op, 1);
7759  op_ia32_Sbb0 = op;
7760  op = new_ir_op(cur_opcode + iro_ia32_Setcc, "ia32_Setcc", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7761  set_op_dump(op, ia32_dump_node);
7762  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7763  set_op_copy_attr(op, be_copy_attr);
7764  set_op_tag(op, ia32_op_tag);
7765  ia32_init_op(op, 1);
7766  op_ia32_Setcc = op;
7767  op = new_ir_op(cur_opcode + iro_ia32_SetccMem, "ia32_SetccMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_condcode_attr_t));
7768  set_op_dump(op, ia32_dump_node);
7769  set_op_attrs_equal(op, ia32_condcode_attrs_equal);
7770  set_op_copy_attr(op, be_copy_attr);
7771  set_op_tag(op, ia32_op_tag);
7772  ia32_init_op(op, 1);
7773  op_ia32_SetccMem = op;
7774  op = new_ir_op(cur_opcode + iro_ia32_Shl, "ia32_Shl", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7775  set_op_dump(op, ia32_dump_node);
7776  set_op_attrs_equal(op, ia32_attrs_equal);
7777  set_op_copy_attr(op, be_copy_attr);
7778  set_op_tag(op, ia32_op_tag);
7779  ia32_init_op(op, 1);
7780  op_ia32_Shl = op;
7781  op = new_ir_op(cur_opcode + iro_ia32_ShlD, "ia32_ShlD", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7782  set_op_dump(op, ia32_dump_node);
7783  set_op_attrs_equal(op, ia32_attrs_equal);
7784  set_op_copy_attr(op, be_copy_attr);
7785  set_op_tag(op, ia32_op_tag);
7786  ia32_init_op(op, 6);
7787  op_ia32_ShlD = op;
7788  op = new_ir_op(cur_opcode + iro_ia32_ShlMem, "ia32_ShlMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7789  set_op_dump(op, ia32_dump_node);
7790  set_op_attrs_equal(op, ia32_attrs_equal);
7791  set_op_copy_attr(op, be_copy_attr);
7792  set_op_tag(op, ia32_op_tag);
7793  ia32_init_op(op, 1);
7794  op_ia32_ShlMem = op;
7795  op = new_ir_op(cur_opcode + iro_ia32_Shr, "ia32_Shr", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7796  set_op_dump(op, ia32_dump_node);
7797  set_op_attrs_equal(op, ia32_attrs_equal);
7798  set_op_copy_attr(op, be_copy_attr);
7799  set_op_tag(op, ia32_op_tag);
7800  ia32_init_op(op, 1);
7801  op_ia32_Shr = op;
7802  op = new_ir_op(cur_opcode + iro_ia32_ShrD, "ia32_ShrD", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7803  set_op_dump(op, ia32_dump_node);
7804  set_op_attrs_equal(op, ia32_attrs_equal);
7805  set_op_copy_attr(op, be_copy_attr);
7806  set_op_tag(op, ia32_op_tag);
7807  ia32_init_op(op, 6);
7808  op_ia32_ShrD = op;
7809  op = new_ir_op(cur_opcode + iro_ia32_ShrMem, "ia32_ShrMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7810  set_op_dump(op, ia32_dump_node);
7811  set_op_attrs_equal(op, ia32_attrs_equal);
7812  set_op_copy_attr(op, be_copy_attr);
7813  set_op_tag(op, ia32_op_tag);
7814  ia32_init_op(op, 1);
7815  op_ia32_ShrMem = op;
7816  op = new_ir_op(cur_opcode + iro_ia32_Stc, "ia32_Stc", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7817  set_op_dump(op, ia32_dump_node);
7818  set_op_attrs_equal(op, ia32_attrs_equal);
7819  set_op_copy_attr(op, be_copy_attr);
7820  set_op_tag(op, ia32_op_tag);
7821  ia32_init_op(op, 1);
7822  op_ia32_Stc = op;
7823  op = new_ir_op(cur_opcode + iro_ia32_Store, "ia32_Store", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_attr_t));
7824  set_op_dump(op, ia32_dump_node);
7825  set_op_attrs_equal(op, ia32_attrs_equal);
7826  set_op_copy_attr(op, be_copy_attr);
7827  ir_op_set_memory_index(op, n_ia32_Store_mem);
7828  ir_op_set_fragile_indices(op, pn_ia32_Store_X_regular, pn_ia32_Store_X_except);
7829  set_op_tag(op, ia32_op_tag);
7830  ia32_init_op(op, 2);
7831  op_ia32_Store = op;
7832  op = new_ir_op(cur_opcode + iro_ia32_Sub, "ia32_Sub", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7833  set_op_dump(op, ia32_dump_node);
7834  set_op_attrs_equal(op, ia32_attrs_equal);
7835  set_op_copy_attr(op, be_copy_attr);
7836  set_op_tag(op, ia32_op_tag);
7837  ia32_init_op(op, 1);
7838  op_ia32_Sub = op;
7839  op = new_ir_op(cur_opcode + iro_ia32_SubMem, "ia32_SubMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7840  set_op_dump(op, ia32_dump_node);
7841  set_op_attrs_equal(op, ia32_attrs_equal);
7842  set_op_copy_attr(op, be_copy_attr);
7843  set_op_tag(op, ia32_op_tag);
7844  ia32_init_op(op, 1);
7845  op_ia32_SubMem = op;
7846  op = new_ir_op(cur_opcode + iro_ia32_SubSP, "ia32_SubSP", op_pin_state_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7847  set_op_dump(op, ia32_dump_node);
7848  set_op_attrs_equal(op, ia32_attrs_equal);
7849  set_op_copy_attr(op, be_copy_attr);
7850  set_op_tag(op, ia32_op_tag);
7851  ia32_init_op(op, 2);
7852  op_ia32_SubSP = op;
7853  op = new_ir_op(cur_opcode + iro_ia32_Subs, "ia32_Subs", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7854  set_op_dump(op, ia32_dump_node);
7855  set_op_attrs_equal(op, ia32_attrs_equal);
7856  set_op_copy_attr(op, be_copy_attr);
7857  set_op_tag(op, ia32_op_tag);
7858  ia32_init_op(op, 4);
7859  op_ia32_Subs = op;
7860  op = new_ir_op(cur_opcode + iro_ia32_SwitchJmp, "ia32_SwitchJmp", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_forking, oparity_any, -1, sizeof(ia32_switch_attr_t));
7861  set_op_dump(op, ia32_dump_node);
7862  set_op_attrs_equal(op, ia32_switch_attrs_equal);
7863  set_op_copy_attr(op, be_copy_attr);
7864  set_op_tag(op, ia32_op_tag);
7865  ia32_init_op(op, 2);
7866  op_ia32_SwitchJmp = op;
7867  op = new_ir_op(cur_opcode + iro_ia32_Test, "ia32_Test", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7868  set_op_dump(op, ia32_dump_node);
7869  set_op_attrs_equal(op, ia32_attrs_equal);
7870  set_op_copy_attr(op, be_copy_attr);
7871  set_op_tag(op, ia32_op_tag);
7872  ia32_init_op(op, 1);
7873  op_ia32_Test = op;
7874  op = new_ir_op(cur_opcode + iro_ia32_UD2, "ia32_UD2", op_pin_state_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7875  set_op_dump(op, ia32_dump_node);
7876  set_op_attrs_equal(op, ia32_attrs_equal);
7877  set_op_copy_attr(op, be_copy_attr);
7878  set_op_tag(op, ia32_op_tag);
7879  ia32_init_op(op, 0);
7880  op_ia32_UD2 = op;
7881  op = new_ir_op(cur_opcode + iro_ia32_Ucomis, "ia32_Ucomis", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7882  set_op_dump(op, ia32_dump_node);
7883  set_op_attrs_equal(op, ia32_attrs_equal);
7884  set_op_copy_attr(op, be_copy_attr);
7885  set_op_tag(op, ia32_op_tag);
7886  ia32_init_op(op, 3);
7887  op_ia32_Ucomis = op;
7888  op = new_ir_op(cur_opcode + iro_ia32_Xor, "ia32_Xor", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7889  set_op_dump(op, ia32_dump_node);
7890  set_op_attrs_equal(op, ia32_attrs_equal);
7891  set_op_copy_attr(op, be_copy_attr);
7892  set_op_tag(op, ia32_op_tag);
7893  ia32_init_op(op, 1);
7894  op_ia32_Xor = op;
7895  op = new_ir_op(cur_opcode + iro_ia32_Xor0, "ia32_Xor0", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
7896  set_op_dump(op, ia32_dump_node);
7897  set_op_attrs_equal(op, ia32_attrs_equal);
7898  set_op_copy_attr(op, be_copy_attr);
7899  set_op_tag(op, ia32_op_tag);
7900  ia32_init_op(op, 1);
7901  op_ia32_Xor0 = op;
7902  op = new_ir_op(cur_opcode + iro_ia32_XorHighLow, "ia32_XorHighLow", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7903  set_op_dump(op, ia32_dump_node);
7904  set_op_attrs_equal(op, ia32_attrs_equal);
7905  set_op_copy_attr(op, be_copy_attr);
7906  set_op_tag(op, ia32_op_tag);
7907  ia32_init_op(op, 1);
7908  op_ia32_XorHighLow = op;
7909  op = new_ir_op(cur_opcode + iro_ia32_XorMem, "ia32_XorMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7910  set_op_dump(op, ia32_dump_node);
7911  set_op_attrs_equal(op, ia32_attrs_equal);
7912  set_op_copy_attr(op, be_copy_attr);
7913  set_op_tag(op, ia32_op_tag);
7914  ia32_init_op(op, 1);
7915  op_ia32_XorMem = op;
7916  op = new_ir_op(cur_opcode + iro_ia32_Xorp, "ia32_Xorp", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7917  set_op_dump(op, ia32_dump_node);
7918  set_op_attrs_equal(op, ia32_attrs_equal);
7919  set_op_copy_attr(op, be_copy_attr);
7920  set_op_tag(op, ia32_op_tag);
7921  ia32_init_op(op, 3);
7922  op_ia32_Xorp = op;
7923  op = new_ir_op(cur_opcode + iro_ia32_emms, "ia32_emms", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_attr_t));
7924  set_op_dump(op, ia32_dump_node);
7925  set_op_attrs_equal(op, attrs_equal_false);
7926  set_op_copy_attr(op, be_copy_attr);
7927  set_op_tag(op, ia32_op_tag);
7928  ia32_init_op(op, 3);
7929  op_ia32_emms = op;
7930  op = new_ir_op(cur_opcode + iro_ia32_fabs, "ia32_fabs", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7931  set_op_dump(op, ia32_dump_node);
7932  set_op_attrs_equal(op, ia32_attrs_equal);
7933  set_op_copy_attr(op, be_copy_attr);
7934  set_op_tag(op, ia32_op_tag);
7935  ia32_init_op(op, 2);
7936  op_ia32_fabs = op;
7937  op = new_ir_op(cur_opcode + iro_ia32_fadd, "ia32_fadd", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7938  set_op_dump(op, ia32_dump_node);
7939  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7940  set_op_copy_attr(op, be_copy_attr);
7941  set_op_tag(op, ia32_op_tag);
7942  ia32_init_op(op, 4);
7943  op_ia32_fadd = op;
7944  op = new_ir_op(cur_opcode + iro_ia32_fchs, "ia32_fchs", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7945  set_op_dump(op, ia32_dump_node);
7946  set_op_attrs_equal(op, ia32_attrs_equal);
7947  set_op_copy_attr(op, be_copy_attr);
7948  set_op_tag(op, ia32_op_tag);
7949  ia32_init_op(op, 2);
7950  op_ia32_fchs = op;
7951  op = new_ir_op(cur_opcode + iro_ia32_fdiv, "ia32_fdiv", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7952  set_op_dump(op, ia32_dump_node);
7953  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7954  set_op_copy_attr(op, be_copy_attr);
7955  set_op_tag(op, ia32_op_tag);
7956  ia32_init_op(op, 20);
7957  op_ia32_fdiv = op;
7958  op = new_ir_op(cur_opcode + iro_ia32_fdup, "ia32_fdup", op_pin_state_floats, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
7959  set_op_dump(op, ia32_dump_node);
7960  set_op_attrs_equal(op, attrs_equal_false);
7961  set_op_copy_attr(op, be_copy_attr);
7962  set_op_tag(op, ia32_op_tag);
7963  ia32_init_op(op, 1);
7964  op_ia32_fdup = op;
7965  op = new_ir_op(cur_opcode + iro_ia32_femms, "ia32_femms", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_attr_t));
7966  set_op_dump(op, ia32_dump_node);
7967  set_op_attrs_equal(op, attrs_equal_false);
7968  set_op_copy_attr(op, be_copy_attr);
7969  set_op_tag(op, ia32_op_tag);
7970  ia32_init_op(op, 3);
7971  op_ia32_femms = op;
7972  op = new_ir_op(cur_opcode + iro_ia32_ffreep, "ia32_ffreep", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_x87_attr_t));
7973  set_op_dump(op, ia32_dump_node);
7974  set_op_attrs_equal(op, attrs_equal_false);
7975  set_op_copy_attr(op, be_copy_attr);
7976  set_op_tag(op, ia32_op_tag);
7977  ia32_init_op(op, 1);
7978  op_ia32_ffreep = op;
7979  op = new_ir_op(cur_opcode + iro_ia32_fild, "ia32_fild", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_attr_t));
7980  set_op_dump(op, ia32_dump_node);
7981  set_op_attrs_equal(op, ia32_attrs_equal);
7982  set_op_copy_attr(op, be_copy_attr);
7983  set_op_tag(op, ia32_op_tag);
7984  ia32_init_op(op, 4);
7985  op_ia32_fild = op;
7986  op = new_ir_op(cur_opcode + iro_ia32_fist, "ia32_fist", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_x87_attr_t));
7987  set_op_dump(op, ia32_dump_node);
7988  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7989  set_op_copy_attr(op, be_copy_attr);
7990  ir_op_set_memory_index(op, n_ia32_fist_mem);
7991  ir_op_set_fragile_indices(op, pn_ia32_fist_X_regular, pn_ia32_fist_X_except);
7992  set_op_tag(op, ia32_op_tag);
7993  ia32_init_op(op, 4);
7994  op_ia32_fist = op;
7995  op = new_ir_op(cur_opcode + iro_ia32_fistp, "ia32_fistp", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_x87_attr_t));
7996  set_op_dump(op, ia32_dump_node);
7997  set_op_attrs_equal(op, ia32_x87_attrs_equal);
7998  set_op_copy_attr(op, be_copy_attr);
7999  ir_op_set_memory_index(op, n_ia32_fistp_mem);
8000  ir_op_set_fragile_indices(op, pn_ia32_fistp_X_regular, pn_ia32_fistp_X_except);
8001  set_op_tag(op, ia32_op_tag);
8002  ia32_init_op(op, 4);
8003  op_ia32_fistp = op;
8004  op = new_ir_op(cur_opcode + iro_ia32_fisttp, "ia32_fisttp", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_x87_attr_t));
8005  set_op_dump(op, ia32_dump_node);
8006  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8007  set_op_copy_attr(op, be_copy_attr);
8008  ir_op_set_memory_index(op, n_ia32_fisttp_mem);
8009  ir_op_set_fragile_indices(op, pn_ia32_fisttp_X_regular, pn_ia32_fisttp_X_except);
8010  set_op_tag(op, ia32_op_tag);
8011  ia32_init_op(op, 4);
8012  op_ia32_fisttp = op;
8013  op = new_ir_op(cur_opcode + iro_ia32_fld, "ia32_fld", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_attr_t));
8014  set_op_dump(op, ia32_dump_node);
8015  set_op_attrs_equal(op, ia32_attrs_equal);
8016  set_op_copy_attr(op, be_copy_attr);
8017  ir_op_set_memory_index(op, n_ia32_fld_mem);
8018  ir_op_set_fragile_indices(op, pn_ia32_fld_X_regular, pn_ia32_fld_X_except);
8019  set_op_tag(op, ia32_op_tag);
8020  ia32_init_op(op, 2);
8021  op_ia32_fld = op;
8022  op = new_ir_op(cur_opcode + iro_ia32_fld1, "ia32_fld1", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8023  set_op_dump(op, ia32_dump_node);
8024  set_op_attrs_equal(op, ia32_attrs_equal);
8025  set_op_copy_attr(op, be_copy_attr);
8026  set_op_tag(op, ia32_op_tag);
8027  ia32_init_op(op, 4);
8028  op_ia32_fld1 = op;
8029  op = new_ir_op(cur_opcode + iro_ia32_fldl2e, "ia32_fldl2e", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8030  set_op_dump(op, ia32_dump_node);
8031  set_op_attrs_equal(op, ia32_attrs_equal);
8032  set_op_copy_attr(op, be_copy_attr);
8033  set_op_tag(op, ia32_op_tag);
8034  ia32_init_op(op, 4);
8035  op_ia32_fldl2e = op;
8036  op = new_ir_op(cur_opcode + iro_ia32_fldl2t, "ia32_fldl2t", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8037  set_op_dump(op, ia32_dump_node);
8038  set_op_attrs_equal(op, ia32_attrs_equal);
8039  set_op_copy_attr(op, be_copy_attr);
8040  set_op_tag(op, ia32_op_tag);
8041  ia32_init_op(op, 4);
8042  op_ia32_fldl2t = op;
8043  op = new_ir_op(cur_opcode + iro_ia32_fldlg2, "ia32_fldlg2", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8044  set_op_dump(op, ia32_dump_node);
8045  set_op_attrs_equal(op, ia32_attrs_equal);
8046  set_op_copy_attr(op, be_copy_attr);
8047  set_op_tag(op, ia32_op_tag);
8048  ia32_init_op(op, 4);
8049  op_ia32_fldlg2 = op;
8050  op = new_ir_op(cur_opcode + iro_ia32_fldln2, "ia32_fldln2", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8051  set_op_dump(op, ia32_dump_node);
8052  set_op_attrs_equal(op, ia32_attrs_equal);
8053  set_op_copy_attr(op, be_copy_attr);
8054  set_op_tag(op, ia32_op_tag);
8055  ia32_init_op(op, 4);
8056  op_ia32_fldln2 = op;
8057  op = new_ir_op(cur_opcode + iro_ia32_fldpi, "ia32_fldpi", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8058  set_op_dump(op, ia32_dump_node);
8059  set_op_attrs_equal(op, ia32_attrs_equal);
8060  set_op_copy_attr(op, be_copy_attr);
8061  set_op_tag(op, ia32_op_tag);
8062  ia32_init_op(op, 4);
8063  op_ia32_fldpi = op;
8064  op = new_ir_op(cur_opcode + iro_ia32_fldz, "ia32_fldz", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8065  set_op_dump(op, ia32_dump_node);
8066  set_op_attrs_equal(op, ia32_attrs_equal);
8067  set_op_copy_attr(op, be_copy_attr);
8068  set_op_tag(op, ia32_op_tag);
8069  ia32_init_op(op, 4);
8070  op_ia32_fldz = op;
8071  op = new_ir_op(cur_opcode + iro_ia32_fmul, "ia32_fmul", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
8072  set_op_dump(op, ia32_dump_node);
8073  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8074  set_op_copy_attr(op, be_copy_attr);
8075  set_op_tag(op, ia32_op_tag);
8076  ia32_init_op(op, 4);
8077  op_ia32_fmul = op;
8078  op = new_ir_op(cur_opcode + iro_ia32_fpop, "ia32_fpop", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_x87_attr_t));
8079  set_op_dump(op, ia32_dump_node);
8080  set_op_attrs_equal(op, attrs_equal_false);
8081  set_op_copy_attr(op, be_copy_attr);
8082  set_op_tag(op, ia32_op_tag);
8083  ia32_init_op(op, 1);
8084  op_ia32_fpop = op;
8085  op = new_ir_op(cur_opcode + iro_ia32_fst, "ia32_fst", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_x87_attr_t));
8086  set_op_dump(op, ia32_dump_node);
8087  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8088  set_op_copy_attr(op, be_copy_attr);
8089  ir_op_set_memory_index(op, n_ia32_fst_mem);
8090  ir_op_set_fragile_indices(op, pn_ia32_fst_X_regular, pn_ia32_fst_X_except);
8091  set_op_tag(op, ia32_op_tag);
8092  ia32_init_op(op, 2);
8093  op_ia32_fst = op;
8094  op = new_ir_op(cur_opcode + iro_ia32_fstp, "ia32_fstp", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_x87_attr_t));
8095  set_op_dump(op, ia32_dump_node);
8096  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8097  set_op_copy_attr(op, be_copy_attr);
8098  ir_op_set_memory_index(op, n_ia32_fstp_mem);
8099  ir_op_set_fragile_indices(op, pn_ia32_fstp_X_regular, pn_ia32_fstp_X_except);
8100  set_op_tag(op, ia32_op_tag);
8101  ia32_init_op(op, 2);
8102  op_ia32_fstp = op;
8103  op = new_ir_op(cur_opcode + iro_ia32_fsub, "ia32_fsub", op_pin_state_exc_pinned, irop_flag_none, oparity_any, -1, sizeof(ia32_x87_attr_t));
8104  set_op_dump(op, ia32_dump_node);
8105  set_op_attrs_equal(op, ia32_x87_attrs_equal);
8106  set_op_copy_attr(op, be_copy_attr);
8107  set_op_tag(op, ia32_op_tag);
8108  ia32_init_op(op, 4);
8109  op_ia32_fsub = op;
8110  op = new_ir_op(cur_opcode + iro_ia32_fxch, "ia32_fxch", op_pin_state_floats, irop_flag_keep, oparity_any, -1, sizeof(ia32_x87_attr_t));
8111  set_op_dump(op, ia32_dump_node);
8112  set_op_attrs_equal(op, attrs_equal_false);
8113  set_op_copy_attr(op, be_copy_attr);
8114  set_op_tag(op, ia32_op_tag);
8115  ia32_init_op(op, 1);
8116  op_ia32_fxch = op;
8117  op = new_ir_op(cur_opcode + iro_ia32_l_Adc, "ia32_l_Adc", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8118  set_op_dump(op, NULL);
8119  set_op_tag(op, ia32_op_tag);
8120  ia32_init_op(op, 0);
8121  op_ia32_l_Adc = op;
8122  op = new_ir_op(cur_opcode + iro_ia32_l_Add, "ia32_l_Add", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8123  set_op_dump(op, NULL);
8124  set_op_tag(op, ia32_op_tag);
8125  ia32_init_op(op, 0);
8126  op_ia32_l_Add = op;
8127  op = new_ir_op(cur_opcode + iro_ia32_l_FloattoLL, "ia32_l_FloattoLL", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8128  set_op_dump(op, NULL);
8129  set_op_tag(op, ia32_op_tag);
8130  ia32_init_op(op, 0);
8131  op_ia32_l_FloattoLL = op;
8132  op = new_ir_op(cur_opcode + iro_ia32_l_IMul, "ia32_l_IMul", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8133  set_op_dump(op, NULL);
8134  set_op_tag(op, ia32_op_tag);
8135  ia32_init_op(op, 0);
8136  op_ia32_l_IMul = op;
8137  op = new_ir_op(cur_opcode + iro_ia32_l_LLtoFloat, "ia32_l_LLtoFloat", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8138  set_op_dump(op, NULL);
8139  set_op_tag(op, ia32_op_tag);
8140  ia32_init_op(op, 0);
8141  op_ia32_l_LLtoFloat = op;
8142  op = new_ir_op(cur_opcode + iro_ia32_l_Minus64, "ia32_l_Minus64", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8143  set_op_dump(op, NULL);
8144  set_op_tag(op, ia32_op_tag);
8145  ia32_init_op(op, 0);
8146  op_ia32_l_Minus64 = op;
8147  op = new_ir_op(cur_opcode + iro_ia32_l_Mul, "ia32_l_Mul", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8148  set_op_dump(op, NULL);
8149  set_op_tag(op, ia32_op_tag);
8150  ia32_init_op(op, 0);
8151  op_ia32_l_Mul = op;
8152  op = new_ir_op(cur_opcode + iro_ia32_l_Sbb, "ia32_l_Sbb", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8153  set_op_dump(op, NULL);
8154  set_op_tag(op, ia32_op_tag);
8155  ia32_init_op(op, 0);
8156  op_ia32_l_Sbb = op;
8157  op = new_ir_op(cur_opcode + iro_ia32_l_Sub, "ia32_l_Sub", op_pin_state_floats, irop_flag_none, oparity_any, -1, 0);
8158  set_op_dump(op, NULL);
8159  set_op_tag(op, ia32_op_tag);
8160  ia32_init_op(op, 0);
8161  op_ia32_l_Sub = op;
8162  op = new_ir_op(cur_opcode + iro_ia32_xAllOnes, "ia32_xAllOnes", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8163  set_op_dump(op, ia32_dump_node);
8164  set_op_attrs_equal(op, ia32_attrs_equal);
8165  set_op_copy_attr(op, be_copy_attr);
8166  set_op_tag(op, ia32_op_tag);
8167  ia32_init_op(op, 3);
8168  op_ia32_xAllOnes = op;
8169  op = new_ir_op(cur_opcode + iro_ia32_xLoad, "ia32_xLoad", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_attr_t));
8170  set_op_dump(op, ia32_dump_node);
8171  set_op_attrs_equal(op, ia32_attrs_equal);
8172  set_op_copy_attr(op, be_copy_attr);
8173  ir_op_set_memory_index(op, n_ia32_xLoad_mem);
8174  ir_op_set_fragile_indices(op, pn_ia32_xLoad_X_regular, pn_ia32_xLoad_X_except);
8175  set_op_tag(op, ia32_op_tag);
8176  ia32_init_op(op, 0);
8177  op_ia32_xLoad = op;
8178  op = new_ir_op(cur_opcode + iro_ia32_xPzero, "ia32_xPzero", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8179  set_op_dump(op, ia32_dump_node);
8180  set_op_attrs_equal(op, ia32_attrs_equal);
8181  set_op_copy_attr(op, be_copy_attr);
8182  set_op_tag(op, ia32_op_tag);
8183  ia32_init_op(op, 3);
8184  op_ia32_xPzero = op;
8185  op = new_ir_op(cur_opcode + iro_ia32_xStore, "ia32_xStore", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_attr_t));
8186  set_op_dump(op, ia32_dump_node);
8187  set_op_attrs_equal(op, ia32_attrs_equal);
8188  set_op_copy_attr(op, be_copy_attr);
8189  ir_op_set_memory_index(op, n_ia32_xStore_mem);
8190  ir_op_set_fragile_indices(op, pn_ia32_xStore_X_regular, pn_ia32_xStore_X_except);
8191  set_op_tag(op, ia32_op_tag);
8192  ia32_init_op(op, 0);
8193  op_ia32_xStore = op;
8194  op = new_ir_op(cur_opcode + iro_ia32_xZero, "ia32_xZero", op_pin_state_floats, irop_flag_constlike, oparity_any, -1, sizeof(ia32_attr_t));
8195  set_op_dump(op, ia32_dump_node);
8196  set_op_attrs_equal(op, ia32_attrs_equal);
8197  set_op_copy_attr(op, be_copy_attr);
8198  set_op_tag(op, ia32_op_tag);
8199  ia32_init_op(op, 3);
8200  op_ia32_xZero = op;
8201  op = new_ir_op(cur_opcode + iro_ia32_xxLoad, "ia32_xxLoad", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_attr_t));
8202  set_op_dump(op, ia32_dump_node);
8203  set_op_attrs_equal(op, ia32_attrs_equal);
8204  set_op_copy_attr(op, be_copy_attr);
8205  ir_op_set_memory_index(op, n_ia32_xxLoad_mem);
8206  ir_op_set_fragile_indices(op, pn_ia32_xxLoad_X_regular, pn_ia32_xxLoad_X_except);
8207  set_op_tag(op, ia32_op_tag);
8208  ia32_init_op(op, 1);
8209  op_ia32_xxLoad = op;
8210  op = new_ir_op(cur_opcode + iro_ia32_xxStore, "ia32_xxStore", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, -1, sizeof(ia32_attr_t));
8211  set_op_dump(op, ia32_dump_node);
8212  set_op_attrs_equal(op, ia32_attrs_equal);
8213  set_op_copy_attr(op, be_copy_attr);
8214  ir_op_set_memory_index(op, n_ia32_xxStore_mem);
8215  ir_op_set_fragile_indices(op, pn_ia32_xxStore_X_regular, pn_ia32_xxStore_X_except);
8216  set_op_tag(op, ia32_op_tag);
8217  ia32_init_op(op, 1);
8218  op_ia32_xxStore = op;
8219 
8220 }
8221 
8222 void ia32_free_opcodes(void)
8223 {
8224  free_ir_op(op_ia32_Adc); op_ia32_Adc = NULL;
8225  free_ir_op(op_ia32_Add); op_ia32_Add = NULL;
8226  free_ir_op(op_ia32_AddMem); op_ia32_AddMem = NULL;
8227  free_ir_op(op_ia32_AddSP); op_ia32_AddSP = NULL;
8228  free_ir_op(op_ia32_Adds); op_ia32_Adds = NULL;
8229  free_ir_op(op_ia32_And); op_ia32_And = NULL;
8230  free_ir_op(op_ia32_AndMem); op_ia32_AndMem = NULL;
8231  free_ir_op(op_ia32_Andnp); op_ia32_Andnp = NULL;
8232  free_ir_op(op_ia32_Andp); op_ia32_Andp = NULL;
8233  free_ir_op(op_ia32_Breakpoint); op_ia32_Breakpoint = NULL;
8234  free_ir_op(op_ia32_Bsf); op_ia32_Bsf = NULL;
8235  free_ir_op(op_ia32_Bsr); op_ia32_Bsr = NULL;
8236  free_ir_op(op_ia32_Bswap); op_ia32_Bswap = NULL;
8237  free_ir_op(op_ia32_Bswap16); op_ia32_Bswap16 = NULL;
8238  free_ir_op(op_ia32_Bt); op_ia32_Bt = NULL;
8239  free_ir_op(op_ia32_CMovcc); op_ia32_CMovcc = NULL;
8240  free_ir_op(op_ia32_Call); op_ia32_Call = NULL;
8241  free_ir_op(op_ia32_ChangeCW); op_ia32_ChangeCW = NULL;
8242  free_ir_op(op_ia32_Cltd); op_ia32_Cltd = NULL;
8243  free_ir_op(op_ia32_Cmc); op_ia32_Cmc = NULL;
8244  free_ir_op(op_ia32_Cmp); op_ia32_Cmp = NULL;
8245  free_ir_op(op_ia32_CmpXChgMem); op_ia32_CmpXChgMem = NULL;
8246  free_ir_op(op_ia32_Const); op_ia32_Const = NULL;
8247  free_ir_op(op_ia32_Conv_FP2FP); op_ia32_Conv_FP2FP = NULL;
8248  free_ir_op(op_ia32_Conv_FP2I); op_ia32_Conv_FP2I = NULL;
8249  free_ir_op(op_ia32_Conv_I2FP); op_ia32_Conv_I2FP = NULL;
8250  free_ir_op(op_ia32_Conv_I2I); op_ia32_Conv_I2I = NULL;
8251  free_ir_op(op_ia32_CopyB); op_ia32_CopyB = NULL;
8252  free_ir_op(op_ia32_CopyB_i); op_ia32_CopyB_i = NULL;
8253  free_ir_op(op_ia32_CopyEbpEsp); op_ia32_CopyEbpEsp = NULL;
8254  free_ir_op(op_ia32_CvtSI2SD); op_ia32_CvtSI2SD = NULL;
8255  free_ir_op(op_ia32_CvtSI2SS); op_ia32_CvtSI2SS = NULL;
8256  free_ir_op(op_ia32_Cwtl); op_ia32_Cwtl = NULL;
8257  free_ir_op(op_ia32_Dec); op_ia32_Dec = NULL;
8258  free_ir_op(op_ia32_DecMem); op_ia32_DecMem = NULL;
8259  free_ir_op(op_ia32_Div); op_ia32_Div = NULL;
8260  free_ir_op(op_ia32_Divs); op_ia32_Divs = NULL;
8261  free_ir_op(op_ia32_Enter); op_ia32_Enter = NULL;
8262  free_ir_op(op_ia32_FldCW); op_ia32_FldCW = NULL;
8263  free_ir_op(op_ia32_FnstCW); op_ia32_FnstCW = NULL;
8264  free_ir_op(op_ia32_FnstCWNOP); op_ia32_FnstCWNOP = NULL;
8265  free_ir_op(op_ia32_FtstFnstsw); op_ia32_FtstFnstsw = NULL;
8266  free_ir_op(op_ia32_FucomFnstsw); op_ia32_FucomFnstsw = NULL;
8267  free_ir_op(op_ia32_Fucomi); op_ia32_Fucomi = NULL;
8268  free_ir_op(op_ia32_FucomppFnstsw); op_ia32_FucomppFnstsw = NULL;
8269  free_ir_op(op_ia32_GetEIP); op_ia32_GetEIP = NULL;
8270  free_ir_op(op_ia32_IDiv); op_ia32_IDiv = NULL;
8271  free_ir_op(op_ia32_IJmp); op_ia32_IJmp = NULL;
8272  free_ir_op(op_ia32_IMul); op_ia32_IMul = NULL;
8273  free_ir_op(op_ia32_IMul1OP); op_ia32_IMul1OP = NULL;
8274  free_ir_op(op_ia32_IMulImm); op_ia32_IMulImm = NULL;
8275  free_ir_op(op_ia32_Immediate); op_ia32_Immediate = NULL;
8276  free_ir_op(op_ia32_Inc); op_ia32_Inc = NULL;
8277  free_ir_op(op_ia32_IncMem); op_ia32_IncMem = NULL;
8278  free_ir_op(op_ia32_Inport); op_ia32_Inport = NULL;
8279  free_ir_op(op_ia32_Jcc); op_ia32_Jcc = NULL;
8280  free_ir_op(op_ia32_Jmp); op_ia32_Jmp = NULL;
8281  free_ir_op(op_ia32_LdTls); op_ia32_LdTls = NULL;
8282  free_ir_op(op_ia32_Lea); op_ia32_Lea = NULL;
8283  free_ir_op(op_ia32_Leave); op_ia32_Leave = NULL;
8284  free_ir_op(op_ia32_Load); op_ia32_Load = NULL;
8285  free_ir_op(op_ia32_Maxs); op_ia32_Maxs = NULL;
8286  free_ir_op(op_ia32_Mins); op_ia32_Mins = NULL;
8287  free_ir_op(op_ia32_Minus64); op_ia32_Minus64 = NULL;
8288  free_ir_op(op_ia32_Movd); op_ia32_Movd = NULL;
8289  free_ir_op(op_ia32_Mul); op_ia32_Mul = NULL;
8290  free_ir_op(op_ia32_Muls); op_ia32_Muls = NULL;
8291  free_ir_op(op_ia32_Neg); op_ia32_Neg = NULL;
8292  free_ir_op(op_ia32_NegMem); op_ia32_NegMem = NULL;
8293  free_ir_op(op_ia32_NoReg_FP); op_ia32_NoReg_FP = NULL;
8294  free_ir_op(op_ia32_NoReg_GP); op_ia32_NoReg_GP = NULL;
8295  free_ir_op(op_ia32_NoReg_XMM); op_ia32_NoReg_XMM = NULL;
8296  free_ir_op(op_ia32_Not); op_ia32_Not = NULL;
8297  free_ir_op(op_ia32_NotMem); op_ia32_NotMem = NULL;
8298  free_ir_op(op_ia32_Or); op_ia32_Or = NULL;
8299  free_ir_op(op_ia32_OrMem); op_ia32_OrMem = NULL;
8300  free_ir_op(op_ia32_Orp); op_ia32_Orp = NULL;
8301  free_ir_op(op_ia32_Outport); op_ia32_Outport = NULL;
8302  free_ir_op(op_ia32_Pop); op_ia32_Pop = NULL;
8303  free_ir_op(op_ia32_PopMem); op_ia32_PopMem = NULL;
8304  free_ir_op(op_ia32_Popcnt); op_ia32_Popcnt = NULL;
8305  free_ir_op(op_ia32_Prefetch); op_ia32_Prefetch = NULL;
8306  free_ir_op(op_ia32_PrefetchNTA); op_ia32_PrefetchNTA = NULL;
8307  free_ir_op(op_ia32_PrefetchT0); op_ia32_PrefetchT0 = NULL;
8308  free_ir_op(op_ia32_PrefetchT1); op_ia32_PrefetchT1 = NULL;
8309  free_ir_op(op_ia32_PrefetchT2); op_ia32_PrefetchT2 = NULL;
8310  free_ir_op(op_ia32_PrefetchW); op_ia32_PrefetchW = NULL;
8311  free_ir_op(op_ia32_Pslld); op_ia32_Pslld = NULL;
8312  free_ir_op(op_ia32_Psllq); op_ia32_Psllq = NULL;
8313  free_ir_op(op_ia32_Psrld); op_ia32_Psrld = NULL;
8314  free_ir_op(op_ia32_Push); op_ia32_Push = NULL;
8315  free_ir_op(op_ia32_PushEax); op_ia32_PushEax = NULL;
8316  free_ir_op(op_ia32_Return); op_ia32_Return = NULL;
8317  free_ir_op(op_ia32_Rol); op_ia32_Rol = NULL;
8318  free_ir_op(op_ia32_RolMem); op_ia32_RolMem = NULL;
8319  free_ir_op(op_ia32_Ror); op_ia32_Ror = NULL;
8320  free_ir_op(op_ia32_RorMem); op_ia32_RorMem = NULL;
8321  free_ir_op(op_ia32_Sahf); op_ia32_Sahf = NULL;
8322  free_ir_op(op_ia32_Sar); op_ia32_Sar = NULL;
8323  free_ir_op(op_ia32_SarMem); op_ia32_SarMem = NULL;
8324  free_ir_op(op_ia32_Sbb); op_ia32_Sbb = NULL;
8325  free_ir_op(op_ia32_Sbb0); op_ia32_Sbb0 = NULL;
8326  free_ir_op(op_ia32_Setcc); op_ia32_Setcc = NULL;
8327  free_ir_op(op_ia32_SetccMem); op_ia32_SetccMem = NULL;
8328  free_ir_op(op_ia32_Shl); op_ia32_Shl = NULL;
8329  free_ir_op(op_ia32_ShlD); op_ia32_ShlD = NULL;
8330  free_ir_op(op_ia32_ShlMem); op_ia32_ShlMem = NULL;
8331  free_ir_op(op_ia32_Shr); op_ia32_Shr = NULL;
8332  free_ir_op(op_ia32_ShrD); op_ia32_ShrD = NULL;
8333  free_ir_op(op_ia32_ShrMem); op_ia32_ShrMem = NULL;
8334  free_ir_op(op_ia32_Stc); op_ia32_Stc = NULL;
8335  free_ir_op(op_ia32_Store); op_ia32_Store = NULL;
8336  free_ir_op(op_ia32_Sub); op_ia32_Sub = NULL;
8337  free_ir_op(op_ia32_SubMem); op_ia32_SubMem = NULL;
8338  free_ir_op(op_ia32_SubSP); op_ia32_SubSP = NULL;
8339  free_ir_op(op_ia32_Subs); op_ia32_Subs = NULL;
8340  free_ir_op(op_ia32_SwitchJmp); op_ia32_SwitchJmp = NULL;
8341  free_ir_op(op_ia32_Test); op_ia32_Test = NULL;
8342  free_ir_op(op_ia32_UD2); op_ia32_UD2 = NULL;
8343  free_ir_op(op_ia32_Ucomis); op_ia32_Ucomis = NULL;
8344  free_ir_op(op_ia32_Xor); op_ia32_Xor = NULL;
8345  free_ir_op(op_ia32_Xor0); op_ia32_Xor0 = NULL;
8346  free_ir_op(op_ia32_XorHighLow); op_ia32_XorHighLow = NULL;
8347  free_ir_op(op_ia32_XorMem); op_ia32_XorMem = NULL;
8348  free_ir_op(op_ia32_Xorp); op_ia32_Xorp = NULL;
8349  free_ir_op(op_ia32_emms); op_ia32_emms = NULL;
8350  free_ir_op(op_ia32_fabs); op_ia32_fabs = NULL;
8351  free_ir_op(op_ia32_fadd); op_ia32_fadd = NULL;
8352  free_ir_op(op_ia32_fchs); op_ia32_fchs = NULL;
8353  free_ir_op(op_ia32_fdiv); op_ia32_fdiv = NULL;
8354  free_ir_op(op_ia32_fdup); op_ia32_fdup = NULL;
8355  free_ir_op(op_ia32_femms); op_ia32_femms = NULL;
8356  free_ir_op(op_ia32_ffreep); op_ia32_ffreep = NULL;
8357  free_ir_op(op_ia32_fild); op_ia32_fild = NULL;
8358  free_ir_op(op_ia32_fist); op_ia32_fist = NULL;
8359  free_ir_op(op_ia32_fistp); op_ia32_fistp = NULL;
8360  free_ir_op(op_ia32_fisttp); op_ia32_fisttp = NULL;
8361  free_ir_op(op_ia32_fld); op_ia32_fld = NULL;
8362  free_ir_op(op_ia32_fld1); op_ia32_fld1 = NULL;
8363  free_ir_op(op_ia32_fldl2e); op_ia32_fldl2e = NULL;
8364  free_ir_op(op_ia32_fldl2t); op_ia32_fldl2t = NULL;
8365  free_ir_op(op_ia32_fldlg2); op_ia32_fldlg2 = NULL;
8366  free_ir_op(op_ia32_fldln2); op_ia32_fldln2 = NULL;
8367  free_ir_op(op_ia32_fldpi); op_ia32_fldpi = NULL;
8368  free_ir_op(op_ia32_fldz); op_ia32_fldz = NULL;
8369  free_ir_op(op_ia32_fmul); op_ia32_fmul = NULL;
8370  free_ir_op(op_ia32_fpop); op_ia32_fpop = NULL;
8371  free_ir_op(op_ia32_fst); op_ia32_fst = NULL;
8372  free_ir_op(op_ia32_fstp); op_ia32_fstp = NULL;
8373  free_ir_op(op_ia32_fsub); op_ia32_fsub = NULL;
8374  free_ir_op(op_ia32_fxch); op_ia32_fxch = NULL;
8375  free_ir_op(op_ia32_l_Adc); op_ia32_l_Adc = NULL;
8376  free_ir_op(op_ia32_l_Add); op_ia32_l_Add = NULL;
8377  free_ir_op(op_ia32_l_FloattoLL); op_ia32_l_FloattoLL = NULL;
8378  free_ir_op(op_ia32_l_IMul); op_ia32_l_IMul = NULL;
8379  free_ir_op(op_ia32_l_LLtoFloat); op_ia32_l_LLtoFloat = NULL;
8380  free_ir_op(op_ia32_l_Minus64); op_ia32_l_Minus64 = NULL;
8381  free_ir_op(op_ia32_l_Mul); op_ia32_l_Mul = NULL;
8382  free_ir_op(op_ia32_l_Sbb); op_ia32_l_Sbb = NULL;
8383  free_ir_op(op_ia32_l_Sub); op_ia32_l_Sub = NULL;
8384  free_ir_op(op_ia32_xAllOnes); op_ia32_xAllOnes = NULL;
8385  free_ir_op(op_ia32_xLoad); op_ia32_xLoad = NULL;
8386  free_ir_op(op_ia32_xPzero); op_ia32_xPzero = NULL;
8387  free_ir_op(op_ia32_xStore); op_ia32_xStore = NULL;
8388  free_ir_op(op_ia32_xZero); op_ia32_xZero = NULL;
8389  free_ir_op(op_ia32_xxLoad); op_ia32_xxLoad = NULL;
8390  free_ir_op(op_ia32_xxStore); op_ia32_xxStore = NULL;
8391 
8392 }
irop_flag_none
Nothing.
Definition: irop.h:43
ir_op_set_memory_index
void ir_op_set_memory_index(ir_op *op, int memory_index)
Sets memory input of operation using memory.
irop_flag_fragile
Set if the operation can change the control flow because of an exception.
Definition: irop.h:46
get_irn_opcode
unsigned get_irn_opcode(const ir_node *node)
Returns the opcode-enum of the node.
irop_flag_forking
Forking control flow at this operation.
Definition: irop.h:49
get_irn_irg
ir_graph * get_irn_irg(const ir_node *node)
Returns the ir_graph this node belongs to.
ir_op
struct ir_op ir_op
Node Opcode.
Definition: firm_types.h:56
set_op_attrs_equal
void set_op_attrs_equal(ir_op *op, node_attrs_equal_func func)
Sets attrs_equal callback func for operation op.
mode_ANY
ir_mode * mode_ANY
undefined mode
Definition: irmode.h:221
verify_new_node
void verify_new_node(ir_node *node)
If firm is built in debug mode, verify that a newly created node is fine.
dbg_info
struct dbg_info dbg_info
Source Reference.
Definition: firm_types.h:40
get_irn_generic_attr
void * get_irn_generic_attr(ir_node *node)
Returns a pointer to the node attributes.
mode_M
ir_mode * mode_M
memory
Definition: irmode.h:190
irop_flag_unknown_jump
This operation jumps to an unknown destination.
Definition: irop.h:59
get_irn_op
ir_op * get_irn_op(const ir_node *node)
Returns the opcode struct of the node.
optimize_node
ir_node * optimize_node(ir_node *n)
Applies local optimizations to a single node.
new_ir_node
ir_node * new_ir_node(dbg_info *db, ir_graph *irg, ir_node *block, ir_op *op, ir_mode *mode, int arity, ir_node *const *in)
IR node constructor.
irop_flag_dump_noblock
node should be dumped outside any blocks
Definition: irop.h:55
irop_flag_cfopcode
This operation is a control flow operation.
Definition: irop.h:45
ir_switch_table
struct ir_switch_table ir_switch_table
A switch table mapping integer numbers to proj-numbers of a Switch-node.
Definition: firm_types.h:102
mode_T
ir_mode * mode_T
tuple (none)
Definition: irmode.h:220
op_pin_state_pinned
Nodes must remain in this basic block.
Definition: firm_types.h:200
irop_flag_keep
This operation can be kept in End&#39;s keep-alive list.
Definition: irop.h:52
irop_flag_uses_memory
This operation has a memory input and may change the memory state.
Definition: irop.h:54
op_pin_state_exc_pinned
Node must remain in this basic block if it can throw an exception, else can float.
Definition: firm_types.h:201
set_op_copy_attr
void set_op_copy_attr(ir_op *op, copy_attr_func func)
Sets attribute copy callback func for operation op.
set_op_hash
void set_op_hash(ir_op *op, hash_func func)
Sets hash callback func for operation op.
oparity_variable
The arity is not fixed by opcode, but statically known.
Definition: irop.h:32
new_ir_op
ir_op * new_ir_op(unsigned code, const char *name, op_pin_state p, irop_flags flags, op_arity opar, int op_index, size_t attr_size)
Creates a new IR operation.
irop_flag_constlike
This operation has no arguments and is some kind of a constant.
Definition: irop.h:50
ir_mode
struct ir_mode ir_mode
SSA Value mode.
Definition: firm_types.h:59
get_next_ir_opcodes
unsigned get_next_ir_opcodes(unsigned num)
Returns the next free n IR opcode number, allows to register a bunch of user ops. ...
set_op_dump
void set_op_dump(ir_op *op, dump_node_func func)
Sets dump callback func for operation op.
ir_entity
struct ir_entity ir_entity
Entity.
Definition: firm_types.h:83
ir_node
struct ir_node ir_node
Procedure Graph Node.
Definition: firm_types.h:53
free_ir_op
void free_ir_op(ir_op *code)
Frees an ir operation.
ir_graph
struct ir_graph ir_graph
Procedure Graph.
Definition: firm_types.h:74
mode_X
ir_mode * mode_X
execution
Definition: irmode.h:217
op_pin_state_floats
Nodes of this opcode can be placed in any basic block.
Definition: firm_types.h:199
oparity_any
Any other arity.
Definition: irop.h:37
ir_op_set_fragile_indices
void ir_op_set_fragile_indices(ir_op *op, unsigned pn_x_regular, unsigned pn_x_except)
Sets proj-number for X_regular and X_except projs of fragile nodes.