gen_arm_regalloc_if.c

#include "gen_arm_regalloc_if.h"

#include "arm_bearch_t.h"

const arch_register_req_t arm_class_reg_req_flags = {
    .cls   = &arm_reg_classes[CLASS_arm_flags],
    .width = 1,
};
static const unsigned arm_limited_flags_fl[] = { (1U << REG_FLAGS_FL) };
const arch_register_req_t arm_single_reg_req_flags_fl = {
    .cls     = &arm_reg_classes[CLASS_arm_flags],
    .limited = arm_limited_flags_fl,
    .width   = 1,
};
const arch_register_req_t arm_class_reg_req_fpa = {
    .cls   = &arm_reg_classes[CLASS_arm_fpa],
    .width = 1,
};
static const unsigned arm_limited_fpa_f0[] = { (1U << REG_FPA_F0) };
const arch_register_req_t arm_single_reg_req_fpa_f0 = {
    .cls     = &arm_reg_classes[CLASS_arm_fpa],
    .limited = arm_limited_fpa_f0,
    .width   = 1,
};
static const unsigned arm_limited_fpa_f1[] = { (1U << REG_FPA_F1) };
const arch_register_req_t arm_single_reg_req_fpa_f1 = {
    .cls     = &arm_reg_classes[CLASS_arm_fpa],
    .limited = arm_limited_fpa_f1,
    .width   = 1,
};
static const unsigned arm_limited_fpa_f2[] = { (1U << REG_FPA_F2) };
const arch_register_req_t arm_single_reg_req_fpa_f2 = {
    .cls     = &arm_reg_classes[CLASS_arm_fpa],
    .limited = arm_limited_fpa_f2,
    .width   = 1,
};
static const unsigned arm_limited_fpa_f3[] = { (1U << REG_FPA_F3) };
const arch_register_req_t arm_single_reg_req_fpa_f3 = {
    .cls     = &arm_reg_classes[CLASS_arm_fpa],
    .limited = arm_limited_fpa_f3,
    .width   = 1,
};
static const unsigned arm_limited_fpa_f4[] = { (1U << REG_FPA_F4) };
const arch_register_req_t arm_single_reg_req_fpa_f4 = {
    .cls     = &arm_reg_classes[CLASS_arm_fpa],
    .limited = arm_limited_fpa_f4,
    .width   = 1,
};
static const unsigned arm_limited_fpa_f5[] = { (1U << REG_FPA_F5) };
const arch_register_req_t arm_single_reg_req_fpa_f5 = {
    .cls     = &arm_reg_classes[CLASS_arm_fpa],
    .limited = arm_limited_fpa_f5,
    .width   = 1,
};
static const unsigned arm_limited_fpa_f6[] = { (1U << REG_FPA_F6) };
const arch_register_req_t arm_single_reg_req_fpa_f6 = {
    .cls     = &arm_reg_classes[CLASS_arm_fpa],
    .limited = arm_limited_fpa_f6,
    .width   = 1,
};
static const unsigned arm_limited_fpa_f7[] = { (1U << REG_FPA_F7) };
const arch_register_req_t arm_single_reg_req_fpa_f7 = {
    .cls     = &arm_reg_classes[CLASS_arm_fpa],
    .limited = arm_limited_fpa_f7,
    .width   = 1,
};
const arch_register_req_t arm_class_reg_req_gp = {
    .cls   = &arm_reg_classes[CLASS_arm_gp],
    .width = 1,
};
static const unsigned arm_limited_gp_r0[] = { (1U << REG_GP_R0) };
const arch_register_req_t arm_single_reg_req_gp_r0 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r0,
    .width   = 1,
};
static const unsigned arm_limited_gp_r1[] = { (1U << REG_GP_R1) };
const arch_register_req_t arm_single_reg_req_gp_r1 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r1,
    .width   = 1,
};
static const unsigned arm_limited_gp_r2[] = { (1U << REG_GP_R2) };
const arch_register_req_t arm_single_reg_req_gp_r2 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r2,
    .width   = 1,
};
static const unsigned arm_limited_gp_r3[] = { (1U << REG_GP_R3) };
const arch_register_req_t arm_single_reg_req_gp_r3 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r3,
    .width   = 1,
};
static const unsigned arm_limited_gp_r4[] = { (1U << REG_GP_R4) };
const arch_register_req_t arm_single_reg_req_gp_r4 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r4,
    .width   = 1,
};
static const unsigned arm_limited_gp_r5[] = { (1U << REG_GP_R5) };
const arch_register_req_t arm_single_reg_req_gp_r5 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r5,
    .width   = 1,
};
static const unsigned arm_limited_gp_r6[] = { (1U << REG_GP_R6) };
const arch_register_req_t arm_single_reg_req_gp_r6 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r6,
    .width   = 1,
};
static const unsigned arm_limited_gp_r7[] = { (1U << REG_GP_R7) };
const arch_register_req_t arm_single_reg_req_gp_r7 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r7,
    .width   = 1,
};
static const unsigned arm_limited_gp_r8[] = { (1U << REG_GP_R8) };
const arch_register_req_t arm_single_reg_req_gp_r8 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r8,
    .width   = 1,
};
static const unsigned arm_limited_gp_r9[] = { (1U << REG_GP_R9) };
const arch_register_req_t arm_single_reg_req_gp_r9 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r9,
    .width   = 1,
};
static const unsigned arm_limited_gp_r10[] = { (1U << REG_GP_R10) };
const arch_register_req_t arm_single_reg_req_gp_r10 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r10,
    .width   = 1,
};
static const unsigned arm_limited_gp_r11[] = { (1U << REG_GP_R11) };
const arch_register_req_t arm_single_reg_req_gp_r11 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r11,
    .width   = 1,
};
static const unsigned arm_limited_gp_r12[] = { (1U << REG_GP_R12) };
const arch_register_req_t arm_single_reg_req_gp_r12 = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_r12,
    .width   = 1,
};
static const unsigned arm_limited_gp_sp[] = { (1U << REG_GP_SP) };
const arch_register_req_t arm_single_reg_req_gp_sp = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_sp,
    .width   = 1,
};
static const unsigned arm_limited_gp_lr[] = { (1U << REG_GP_LR) };
const arch_register_req_t arm_single_reg_req_gp_lr = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_lr,
    .width   = 1,
};
static const unsigned arm_limited_gp_pc[] = { (1U << REG_GP_PC) };
const arch_register_req_t arm_single_reg_req_gp_pc = {
    .cls     = &arm_reg_classes[CLASS_arm_gp],
    .limited = arm_limited_gp_pc,
    .width   = 1,
};


arch_register_class_t arm_reg_classes[] = {
    {
        .name      = "arm_flags",
        .mode      = NULL,
        .regs      = &arm_registers[REG_FL],
        .class_req = &arm_class_reg_req_flags,
        .index     = CLASS_arm_flags,
        .n_regs    = 1,
        .manual_ra = true,
    },
    {
        .name      = "arm_fpa",
        .mode      = NULL,
        .regs      = &arm_registers[REG_F0],
        .class_req = &arm_class_reg_req_fpa,
        .index     = CLASS_arm_fpa,
        .n_regs    = 8,
        .manual_ra = false,
    },
    {
        .name      = "arm_gp",
        .mode      = NULL,
        .regs      = &arm_registers[REG_R0],
        .class_req = &arm_class_reg_req_gp,
        .index     = CLASS_arm_gp,
        .n_regs    = 16,
        .manual_ra = false,
    },

};

const arch_register_t arm_registers[] = {
    {
        .name         = "fl",
        .cls          = &arm_reg_classes[CLASS_arm_flags],
        .single_req   = &arm_single_reg_req_flags_fl,
        .index        = REG_FLAGS_FL,
        .global_index = REG_FL,
        .dwarf_number = 0,
        .encoding     = REG_FLAGS_FL,
        .is_virtual   = false,
    },
    {
        .name         = "f0",
        .cls          = &arm_reg_classes[CLASS_arm_fpa],
        .single_req   = &arm_single_reg_req_fpa_f0,
        .index        = REG_FPA_F0,
        .global_index = REG_F0,
        .dwarf_number = 96,
        .encoding     = REG_FPA_F0,
        .is_virtual   = false,
    },
    {
        .name         = "f1",
        .cls          = &arm_reg_classes[CLASS_arm_fpa],
        .single_req   = &arm_single_reg_req_fpa_f1,
        .index        = REG_FPA_F1,
        .global_index = REG_F1,
        .dwarf_number = 97,
        .encoding     = REG_FPA_F1,
        .is_virtual   = false,
    },
    {
        .name         = "f2",
        .cls          = &arm_reg_classes[CLASS_arm_fpa],
        .single_req   = &arm_single_reg_req_fpa_f2,
        .index        = REG_FPA_F2,
        .global_index = REG_F2,
        .dwarf_number = 98,
        .encoding     = REG_FPA_F2,
        .is_virtual   = false,
    },
    {
        .name         = "f3",
        .cls          = &arm_reg_classes[CLASS_arm_fpa],
        .single_req   = &arm_single_reg_req_fpa_f3,
        .index        = REG_FPA_F3,
        .global_index = REG_F3,
        .dwarf_number = 99,
        .encoding     = REG_FPA_F3,
        .is_virtual   = false,
    },
    {
        .name         = "f4",
        .cls          = &arm_reg_classes[CLASS_arm_fpa],
        .single_req   = &arm_single_reg_req_fpa_f4,
        .index        = REG_FPA_F4,
        .global_index = REG_F4,
        .dwarf_number = 100,
        .encoding     = REG_FPA_F4,
        .is_virtual   = false,
    },
    {
        .name         = "f5",
        .cls          = &arm_reg_classes[CLASS_arm_fpa],
        .single_req   = &arm_single_reg_req_fpa_f5,
        .index        = REG_FPA_F5,
        .global_index = REG_F5,
        .dwarf_number = 101,
        .encoding     = REG_FPA_F5,
        .is_virtual   = false,
    },
    {
        .name         = "f6",
        .cls          = &arm_reg_classes[CLASS_arm_fpa],
        .single_req   = &arm_single_reg_req_fpa_f6,
        .index        = REG_FPA_F6,
        .global_index = REG_F6,
        .dwarf_number = 102,
        .encoding     = REG_FPA_F6,
        .is_virtual   = false,
    },
    {
        .name         = "f7",
        .cls          = &arm_reg_classes[CLASS_arm_fpa],
        .single_req   = &arm_single_reg_req_fpa_f7,
        .index        = REG_FPA_F7,
        .global_index = REG_F7,
        .dwarf_number = 103,
        .encoding     = REG_FPA_F7,
        .is_virtual   = false,
    },
    {
        .name         = "r0",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r0,
        .index        = REG_GP_R0,
        .global_index = REG_R0,
        .dwarf_number = 0,
        .encoding     = REG_GP_R0,
        .is_virtual   = false,
    },
    {
        .name         = "r1",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r1,
        .index        = REG_GP_R1,
        .global_index = REG_R1,
        .dwarf_number = 1,
        .encoding     = REG_GP_R1,
        .is_virtual   = false,
    },
    {
        .name         = "r2",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r2,
        .index        = REG_GP_R2,
        .global_index = REG_R2,
        .dwarf_number = 2,
        .encoding     = REG_GP_R2,
        .is_virtual   = false,
    },
    {
        .name         = "r3",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r3,
        .index        = REG_GP_R3,
        .global_index = REG_R3,
        .dwarf_number = 3,
        .encoding     = REG_GP_R3,
        .is_virtual   = false,
    },
    {
        .name         = "r4",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r4,
        .index        = REG_GP_R4,
        .global_index = REG_R4,
        .dwarf_number = 4,
        .encoding     = REG_GP_R4,
        .is_virtual   = false,
    },
    {
        .name         = "r5",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r5,
        .index        = REG_GP_R5,
        .global_index = REG_R5,
        .dwarf_number = 5,
        .encoding     = REG_GP_R5,
        .is_virtual   = false,
    },
    {
        .name         = "r6",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r6,
        .index        = REG_GP_R6,
        .global_index = REG_R6,
        .dwarf_number = 6,
        .encoding     = REG_GP_R6,
        .is_virtual   = false,
    },
    {
        .name         = "r7",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r7,
        .index        = REG_GP_R7,
        .global_index = REG_R7,
        .dwarf_number = 7,
        .encoding     = REG_GP_R7,
        .is_virtual   = false,
    },
    {
        .name         = "r8",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r8,
        .index        = REG_GP_R8,
        .global_index = REG_R8,
        .dwarf_number = 8,
        .encoding     = REG_GP_R8,
        .is_virtual   = false,
    },
    {
        .name         = "r9",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r9,
        .index        = REG_GP_R9,
        .global_index = REG_R9,
        .dwarf_number = 9,
        .encoding     = REG_GP_R9,
        .is_virtual   = false,
    },
    {
        .name         = "r10",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r10,
        .index        = REG_GP_R10,
        .global_index = REG_R10,
        .dwarf_number = 10,
        .encoding     = REG_GP_R10,
        .is_virtual   = false,
    },
    {
        .name         = "r11",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r11,
        .index        = REG_GP_R11,
        .global_index = REG_R11,
        .dwarf_number = 11,
        .encoding     = REG_GP_R11,
        .is_virtual   = false,
    },
    {
        .name         = "r12",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_r12,
        .index        = REG_GP_R12,
        .global_index = REG_R12,
        .dwarf_number = 12,
        .encoding     = REG_GP_R12,
        .is_virtual   = false,
    },
    {
        .name         = "sp",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_sp,
        .index        = REG_GP_SP,
        .global_index = REG_SP,
        .dwarf_number = 13,
        .encoding     = REG_GP_SP,
        .is_virtual   = false,
    },
    {
        .name         = "lr",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_lr,
        .index        = REG_GP_LR,
        .global_index = REG_LR,
        .dwarf_number = 14,
        .encoding     = REG_GP_LR,
        .is_virtual   = false,
    },
    {
        .name         = "pc",
        .cls          = &arm_reg_classes[CLASS_arm_gp],
        .single_req   = &arm_single_reg_req_gp_pc,
        .index        = REG_GP_PC,
        .global_index = REG_PC,
        .dwarf_number = 15,
        .encoding     = REG_GP_PC,
        .is_virtual   = false,
    },

};

void arm_register_init(void)
{
    arm_reg_classes[CLASS_arm_flags].mode = arm_mode_flags;
    arm_reg_classes[CLASS_arm_fpa].mode = mode_F;
    arm_reg_classes[CLASS_arm_gp].mode = arm_mode_gp;

}